公开(公告)号：US20240120403A1

公开(公告)日：2024-04-11

申请号：US18481444

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeeun YANG ,  Sangwook KIM ,  Euntae KIM ,  Kwanghee LEE ,  Moonil JUNG

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/443 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/443 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a lower electrode on a substrate, a metal oxide on the lower electrode, a buffer on the metal oxide, an oxide channel in the buffer, a gate insulating layer in the oxide channel, a gate electrode in the gate insulating layer, and an upper electrode on the gate electrode, and the buffer may include a silicide material.

公开(公告)号：US20240215215A1

公开(公告)日：2024-06-27

申请号：US18534220

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Kwanghee LEE ,  Jeeeun YANG ,  Moonil JUNG ,  Euntae KIM ,  Youngkwan CHA

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A memory device includes a read word line on a substrate, a first channel extending along a plane perpendicular to an upper surface of the substrate, a second channel facing the first channel in parallel, a first gate insulation layer adjacent to the first channel between the first channel and the second channel, a second gate insulation layer adjacent to the second channel between the first channel and the second channel, a gate electrode adjacent to the first gate insulation layer between the first gate insulation layer and the second gate insulation layer, a write word line adjacent to the second gate insulation layer between the first gate insulation layer and the second gate insulation layer, a read bit line electrically connected to the first channel, and a write bit line electrically connected to the second channel.

公开(公告)号：US20240120421A1

公开(公告)日：2024-04-11

申请号：US18479428

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeeun YANG ,  Sangwook KIM ,  Euntae KIM ,  Kwanghee LEE ,  Moonil JUNG

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/66742

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a lower electrode provided on a substrate, a buffer layer provided on the lower electrode and including first indium, an oxide semiconductor layer provided on the buffer layer and including second indium, a gate electrode provided apart from the oxide semiconductor layer, and an upper electrode provided on the oxide semiconductor layer, wherein a content of the first indium is greater than a content of the second indium.

公开(公告)号：US20240162350A1

公开(公告)日：2024-05-16

申请号：US18496353

申请日：2023-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonil JUNG ,  Sangwook KIM ,  Euntae KIM ,  Jeeeun YANG ,  Kwanghee LEE ,  Youngkwan CHA

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/1054 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: Semiconductor devices and manufacturing methods thereof are provided. A semiconductor device includes a substrate, a lower electrode on the substrate, an oxide channel on the lower electrode, the oxide channel including vertical extension portions extending in a first direction perpendicular to the substrate, an upper electrode on the oxide channel, a gate insulator on a portion the oxide channel that is exposed by the lower electrode and the upper electrode, and a gate electrode on the gate insulator, wherein the upper electrode and the lower electrode are separated from each other by the oxide channel in the first direction, and the oxide channel is doped with ions.

公开(公告)号：US20240079468A1

公开(公告)日：2024-03-07

申请号：US18457803

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonil JUNG ,  Sangwook KIM ,  Euntae KIM ,  Jeeeun YANG ,  Kwanghee LEE

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78642 ,  H01L29/7869 ,  H01L21/02491 ,  H01L29/78696

Abstract: Provided are a vertical transistor and a method of manufacturing the same. The vertical transistor includes a substrate, a lower electrode on the substrate and including a metal material, a carbon thin film being conductive and on the lower electrode, an oxide semiconductor layer on the carbon thin film, a gate electrode apart from the oxide semiconductor layer, a gate insulating layer arranged between the oxide semiconductor layer and the gate electrode, and an upper electrode on the oxide semiconductor layer, wherein the lower electrode. The carbon thin film, the oxide semiconductor layer, and the upper electrode are arranged in a direction perpendicular to the substrate.

公开(公告)号：US20230051857A1

公开(公告)日：2023-02-16

申请号：US17540662

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM ,  Euntae KIM ,  Jeeeun YANG ,  Moonil JUNG ,  Sangjun HONG

IPC: H01L29/786 ,  H01L29/417

Abstract: Provided are oxide semiconductor transistors. The oxide semiconductor transistor includes a substrate, a channel layer arranged on the substrate and having a flat plate shape extending along one plane, a gate electrode facing a part of the channel layer, and a source region and a drain region separated from each other with the gate electrode therebetween, wherein the source region contacts three or more surfaces of the channel layer, and the drain region contacts three or more surfaces of the channel layer.