公开(公告)号：US20240040792A1

公开(公告)日：2024-02-01

申请号：US18356324

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngshik Yun ,  Dongsik Lee ,  Siwan Kim ,  Sori Lee ,  Bongtae Park ,  Jaejoo Shim

IPC: H10B43/40 ,  H10B43/27 ,  H10B43/35 ,  H10B41/40 ,  H10B41/27 ,  H10B41/35 ,  G11C16/04 ,  H01L23/528 ,  H10B80/00 ,  H01L25/065

CPC classification number: H10B43/40 ,  H10B43/27 ,  H10B43/35 ,  H10B41/40 ,  H10B41/27 ,  H10B41/35 ,  G11C16/0483 ,  H01L23/5283 ,  H10B80/00 ,  H01L25/0652 ,  H01L2225/06541

Abstract: A semiconductor device includes a peripheral circuit region and a memory cell region. The memory cell region may include a stack structure including gate electrodes and interlayer insulating layers repeatedly and alternately stacked in a vertical direction, and a channel structure penetrating through the stack structure. The gate electrodes may include first gate electrodes, second gate electrodes on the first gate electrodes, and third gate electrodes on the second gate electrodes. Each of the first gate electrodes may have a first thickness. Each of the second gate electrodes may have a second thickness that is greater than the first thickness. Each of the third gate electrodes may have a third thickness that is smaller than the second thickness.