公开(公告)号：US20240040792A1

公开(公告)日：2024-02-01

申请号：US18356324

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngshik Yun ,  Dongsik Lee ,  Siwan Kim ,  Sori Lee ,  Bongtae Park ,  Jaejoo Shim

IPC: H10B43/40 ,  H10B43/27 ,  H10B43/35 ,  H10B41/40 ,  H10B41/27 ,  H10B41/35 ,  G11C16/04 ,  H01L23/528 ,  H10B80/00 ,  H01L25/065

CPC classification number: H10B43/40 ,  H10B43/27 ,  H10B43/35 ,  H10B41/40 ,  H10B41/27 ,  H10B41/35 ,  G11C16/0483 ,  H01L23/5283 ,  H10B80/00 ,  H01L25/0652 ,  H01L2225/06541

Abstract: A semiconductor device includes a peripheral circuit region and a memory cell region. The memory cell region may include a stack structure including gate electrodes and interlayer insulating layers repeatedly and alternately stacked in a vertical direction, and a channel structure penetrating through the stack structure. The gate electrodes may include first gate electrodes, second gate electrodes on the first gate electrodes, and third gate electrodes on the second gate electrodes. Each of the first gate electrodes may have a first thickness. Each of the second gate electrodes may have a second thickness that is greater than the first thickness. Each of the third gate electrodes may have a third thickness that is smaller than the second thickness.

公开(公告)号：US11233062B2

公开(公告)日：2022-01-25

申请号：US16827778

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Kim ,  Jaehoon Lee ,  Jiyoung Kim ,  Bongtae Park ,  Jaejoo Shim

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US11637110B2

公开(公告)日：2023-04-25

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Kim ,  Jaehoon Lee ,  Jiyoung Kim ,  Bongtae Park ,  Jaejoo Shim

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20220415915A1

公开(公告)日：2022-12-29

申请号：US17747462

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN HWANG ,  Jaejoo Shim ,  Bongtae Park ,  Taechul Jung ,  Jongyoon Choi

IPC: H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

Abstract: Semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, separation regions penetrating the gate electrodes, extending in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, channel structures arranged in columns in the third direction and rows in the second direction and penetrating the gate electrodes between the separation regions, and bit lines extending in the third direction on the channel structures. The channel structures include a first group of channel structures repeatedly arranged and including three columns arranged with a first pitch and a second pitch smaller than the first pitch in order, and the bit lines are arranged with at least one pitch smaller than the second pitch in the second direction.