-
公开(公告)号：US20150067895A1
公开(公告)日：2015-03-05
申请号：US14460982
申请日：2014-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ihor VASYLTSOV , Karpinskyy BOHDAN , Kalesnikau ALIAKSEI , Yun-hyeok CHOI
CPC classification number: H04L9/3278 , G06F21/73
Abstract: The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable PUF by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone.In various embodiments of the inventive concept, the blind zone is generated only in a period when a reset signal is at a first logic level. Therefore, it is possible to minimize the blind zone by minimizing a period in which the reset signal is at such logic level. A semiconductor device, semiconductor package, and/or smart card can be provided with such security device, as well as a method for determining a validity of a random signal using a semiconductor security device.
Abstract translation: 本发明的概念提供了一种安全装置，其能够通过从预定义数量的熵源增加熵值和/或最小化有效性检查模块的盲区来减少实现稳定PUF所需的裸片的面积。 安全设备使用异步配置来最小化盲区。 在本发明构思的各种实施例中，盲区仅在复位信号处于第一逻辑电平的时段内产生。 因此，可以通过使复位信号处于这样的逻辑电平的周期最小化来最小化盲区。 半导体器件，半导体封装和/或智能卡可以设置有这种安全装置，以及使用半导体安全装置确定随机信号的有效性的方法。
-
Patent Agency Ranking
公开(公告)号：US20200099542A1
公开(公告)日：2020-03-26
申请号：US16677901
申请日：2019-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ihor VASYLTSOV , Karpinskyy BOHDAN , Kalesnikau ALIAKSEI , Yun-hyeok CHOI
Abstract: The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable PUF by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone. In various embodiments of the inventive concept, the blind zone is generated only in a period when a reset signal is at a first logic level. Therefore, it is possible to minimize the blind zone by minimizing a period in which the reset signal is at such logic level. A semiconductor device, semiconductor package, and/or smart card can be provided with such security device, as well as a method for determining a validity of a random signal using a semiconductor security device.
-
公开(公告)号：US20180302229A1
公开(公告)日：2018-10-18
申请号：US16021494
申请日：2018-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ihor VASYLTSOV , Karpinskyy BOHDAN , Kalesnikau ALIAKSEI , Yun-hyeok CHOI
Abstract: The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable PUF by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone. In various embodiments of the inventive concept, the blind zone is generated only in a period when a reset signal is at a first logic level. Therefore, it is possible to minimize the blind zone by minimizing a period in which the reset signal is at such logic level. A semiconductor device, semiconductor package, and/or smart card can be provided with such security device, as well as a method for determining a validity of a random signal using a semiconductor security device.
-
公开(公告)号：US20200159497A1
公开(公告)日：2020-05-21
申请号：US16541705
申请日：2019-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-eun PARK , Yong-ki LEE , Yun-hyeok CHOI , Bohdan KARPINSKYY
Abstract: A random number generator including: a first ring oscillator including a first inverter chain, the first inverter chain including a plurality of serially connected first inverters, the first ring oscillator configured to output a first random signal generated at a first sub-node between two neighboring first inverters among the plurality of first inverters; a second ring oscillator including a second inverter chain, the second inverter chain including a plurality of serially connected second inverters, the second ring oscillator configured to output a second random signal generated at a second sub-node between two neighboring second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal with the second random signal.
-
公开(公告)号：US20190068190A1
公开(公告)日：2019-02-28
申请号：US16004517
申请日：2018-06-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bohdan KARPINSKYY , Dae-hyeon KIM , Mi-jung NOH , Sang-wook PARK , Yong-ki LEE , Yun-hyeok CHOI
IPC: H03K19/003 , H04L9/08 , H01L23/00
CPC classification number: H03K19/003 , G06F7/588 , H01L23/576 , H04L9/0866 , H04L9/0869 , H04L9/3278
Abstract: An integrated circuit for a physically unclonable function (PUF) includes first and second PUF cells and a combination circuit. The first and second PUF cells respectively output first and second cell signals having unique levels based on a threshold level of a logic gate. The combination circuit includes a first stage that generates a first combination signal based on the first and second cell signals. The first and second PUF cells respectively include first and second logic gates to respectively output the first and second cell signals. The combination circuit includes a third logic gate that receives the first and second cell signals and outputs the first combination signal. The third logic gate has a same structure as each of the first and second logic gates.
-
公开(公告)号：US20180136907A1
公开(公告)日：2018-05-17
申请号：US15404826
申请日：2017-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Karpinskyy BOHDAN , Yong-ki LEE , Mi-jung NOH , Sang-wook PARK , Ki-tak KIM , Yong-Soo KIM , Yun-hyeok CHOI
IPC: G06F7/58
Abstract: An apparatus for testing a random number generator includes a correlation test circuit and a randomness determination circuit. The correlation test circuit extracts a first plurality of bit pairs each including two bits spaced apart from each other by a first distance in a bit stream generated by the random number generator, obtains a first sum of differences between respective two bits of the first plurality of bit pairs, and obtains a second sum of differences between respective two bits of a second plurality of bit pairs, the second plurality of bit pairs each including two bits spaced apart from each other by a second distance, different from the first distance, in the bit stream. The randomness determination circuit determines a randomness of the bit stream, based on the first sum and the second sum.
-
-
-
-
-
Search Results
6
records
(took 0.019 seconds)
