-
1.发明授权公开(公告)号：US07925948B2
公开(公告)日：2011-04-12
申请号：US12206789
申请日：2008-09-09
IPC分类号： G01R31/28
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译： 一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。 不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位 模式。 电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。 测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。
-
2.发明申请System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits 有权通过电力方面的功率降低系统和方法，复杂子电路的锁存加权公开(公告)号：US20100064190A1
公开(公告)日：2010-03-11
申请号：US12206781
申请日：2008-09-09
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译： 一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。 电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。 不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。 子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。 子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。
-
3.发明申请公开(公告)号：US20100064189A1
公开(公告)日：2010-03-11
申请号：US12206789
申请日：2008-09-09
IPC分类号： G06F11/00
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译： 一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。 不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位 模式。 电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。 测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。
-
4.发明授权System and method for power reduction through power aware latch weighting of complex sub-circuits 有权通过复杂子电路的功率感知锁存器加权降低功耗的系统和方法公开(公告)号：US07930610B2
公开(公告)日：2011-04-19
申请号：US12206781
申请日：2008-09-09
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译： 一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。 电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。 不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。 子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。 子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。
-
公开(公告)号：US08140903B2
公开(公告)日：2012-03-20
申请号：US12425075
申请日：2009-04-16
IPC分类号： G06F11/00
CPC分类号： G06F11/349 , G06F2201/87
摘要： A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
摘要翻译： 用于在多处理器系统中跟踪线程总线事务的方法包括由处理器解码线程的第一线程指令，所述线程包括有序序列的线程指令。 在第一个线程指令是一个设置的总线跟踪使能位（BTEB）指令的情况下，处理器设置与线程相对应的总线跟踪使能位。 在设置BTEB的情况下，处理器确定第一个线程指令是否是符合条件的指令，并且在第一个线程指令是符合跟踪条件的指令的情况下，并且BTEB被设置，处理器设置一个窥探标记 跟踪使能位（STTEB）。 硬件跟踪监视器（HTM）监视总线事务，每个总线事务包括STTE。 在监控总线事务包括一组STTEB的情况下，HTM将总线事务存储为跟踪数据。 在监控总线事务包括复位STTEB的情况下，HTM不将总线事务存储为跟踪数据。
-
公开(公告)号：US20100268995A1
公开(公告)日：2010-10-21
申请号：US12425075
申请日：2009-04-16
IPC分类号： G06F11/07
CPC分类号： G06F11/349 , G06F2201/87
摘要： A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
摘要翻译： 用于在多处理器系统中跟踪线程总线事务的方法包括由处理器解码线程的第一线程指令，所述线程包括有序序列的线程指令。 在第一个线程指令是一个设置的总线跟踪使能位（BTEB）指令的情况下，处理器设置与线程相对应的总线跟踪使能位。 在设置BTEB的情况下，处理器确定第一个线程指令是否是符合条件的指令，并且在第一个线程指令是符合跟踪条件的指令的情况下，并且BTEB被设置，处理器设置一个窥探标记 跟踪使能位（STTEB）。 硬件跟踪监视器（HTM）监视总线事务，每个总线事务包括STTE。 在监控总线事务包括一组STTEB的情况下，HTM将总线事务存储为跟踪数据。 在监控总线事务包括复位STTEB的情况下，HTM不将总线事务存储为跟踪数据。
-
7.发明授权公开(公告)号：US08234612B2
公开(公告)日：2012-07-31
申请号：US12862949
申请日：2010-08-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译： 通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元 具有最高备用利用率的区域。 使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。 由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。 备用单元插入具有最多边缘的区域（边缘可以加权）。 该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。
-
8.发明申请CONE-AWARE SPARE CELL PLACEMENT USING HYPERGRAPH CONNECTIVITY ANALYSIS 有权使用HYPERGRAPH连接分析的CONE-AWARE SPARE CELL PLACEMENT公开(公告)号：US20120054707A1
公开(公告)日：2012-03-01
申请号：US12862949
申请日：2010-08-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译： 通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元 具有最高备用利用率的区域。 使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。 由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。 备用单元插入具有最多边缘的区域（边缘可以加权）。 该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。
-
公开(公告)号：US08793636B2
公开(公告)日：2014-07-29
申请号：US13086428
申请日：2011-04-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.
摘要翻译： 提供了用于在半导体器件的设计中执行电池放置的机构。 生成半导体器件的初始设计，初始设计包括单元的第一放置。 确定与细胞相关联的放置的优选方向。 优选的方向是细胞扩散优选的方向。 基于与单元相关联的放置的优选方向，通过修改单元的第一放置以产生与第一放置单元不同的单元的第二放置来生成半导体器件的第二设计。
-
公开(公告)号：US08214170B2
公开(公告)日：2012-07-03
申请号：US12354063
申请日：2009-01-15
IPC分类号： G01R31/14
CPC分类号： G01R31/318547
摘要： A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.
摘要翻译： 测试图案压缩的方法产生包括多个位的第一测试图案。 该方法识别在第一测试模式中包含不关心位值的位，并且用随机位值替换所识别的位值，以产生第二测试模式。 该方法确定第二测试模式的故障覆盖水平。 在第二测试模式的所确定的故障覆盖水平超过预定的单独测试模式故障覆盖水平的情况下，对于与替换的所识别的位值相对应的第二测试模式中的至少一个位位置并检测至少一个故障，该方法 在第一测试模式中的位位置交换不关心值的第二测试模式中相应位位置的位值。 该方法将随后的测试模式合并，以增加第二个测试模式的故障覆盖。
-
-
-
-
-
-
-
-
-
搜索结果
51 条记录 (耗时 0.026 秒)
