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公开(公告)号：US11081192B2
公开(公告)日：2021-08-03
申请号：US16668949
申请日：2019-10-30
发明人： Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Yuki Fujita , Naoki Ookuma , Kazuki Yamauchi , Masahito Takehara , Toru Miwa
摘要： A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
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公开(公告)号：US20210134375A1
公开(公告)日：2021-05-06
申请号：US16668949
申请日：2019-10-30
发明人： Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Yuki Fujita , Naoki Ookuma , Kazuki Yamauchi , Masahito Takehara , Toru Miwa
摘要： A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
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公开(公告)号：US10885984B1
公开(公告)日：2021-01-05
申请号：US16668073
申请日：2019-10-30
发明人： Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Yuki Fujita , Naoki Ookuma , Kazuki Yamauchi , Masahito Takehara , Toru Miwa
IPC分类号： G11C16/04 , G11C16/14 , H01L27/11524
摘要： A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
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公开(公告)号：US11573914B2
公开(公告)日：2023-02-07
申请号：US17206864
申请日：2021-03-19
发明人： Hiroki Yabe , Masahito Takehara
摘要： A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.
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公开(公告)号：US20220300162A1
公开(公告)日：2022-09-22
申请号：US17206864
申请日：2021-03-19
发明人： Hiroki Yabe , Masahito Takehara
摘要： A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.
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