公开(公告)号：US07132965B2

公开(公告)日：2006-11-07

申请号：US11284985

申请日：2005-11-21

申请人： Sandeep Kumar Gupta ,  Oleksly Zabroda

发明人： Sandeep Kumar Gupta ,  Oleksly Zabroda

IPC分类号： H03M1/00

CPC分类号： G11C27/024 ,  H03M1/1215 ,  H03M1/1245

摘要： A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i−1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i−1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

摘要翻译： 公开了一种高速采样系统和模数转换器。 对信号进行采样的方法的一个实施例包括接收模拟信号并以F s的速率产生第一采样，并以Fs / N的速率从第一采样产生第二子采样，并具有大约（360 / N）*（i-1）度，其中i从1变化到N.在第一实施例中，至多两个第二子采样器在任何时间点跟踪第一采样器的输出。 在第二实施例中，N个第二子采样器中的仅一个在任何时间点跟踪第一采样器的输出。 第三实施例还包括以Fs / N的速率从第二样本产生第三样本，并且具有近似（（360 / N）*（i-1）+180）度的相对相位。 交错模数转换的方法包括接收第三样本的对应的时间交织ADC。

公开(公告)号：US12021029B2

公开(公告)日：2024-06-25

申请号：US17676761

申请日：2022-02-21

申请人： Sandeep Kumar Gupta

发明人： Sandeep Kumar Gupta

IPC分类号： G06F1/18 ,  H01L23/528

CPC分类号： H01L23/5286 ,  G06F1/189

摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M−1.

公开(公告)号：US08138839B2

公开(公告)日：2012-03-20

申请号：US11783601

申请日：2007-04-10

申请人： Sandeep Kumar Gupta ,  Venugopal Gopinathan

发明人： Sandeep Kumar Gupta ,  Venugopal Gopinathan

IPC分类号： H03F3/04

CPC分类号： H03F1/52 ,  H03F1/523 ,  H03F3/45085 ,  H03F3/45183 ,  H03F2200/447 ,  H03F2203/45288 ,  H03F2203/45292 ,  H03F2203/45324 ,  H03F2203/45336 ,  H03F2203/45398 ,  H03F2203/45696 ,  H03F2203/45722

摘要： A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

摘要翻译： CMOS增益级包括偏置电路，其配置成在没有源极跟随器电路的情况下确保后续级的饱和。 CMOS增益级可选择用于制造CMOS增益级的工艺技术的电源电压大于允许的电源电压。 为了保护CMOS增益级中的CMOS器件，公开了可选的漏极到体结结穿通保护电路。 各种可选特征可以单独实现和/或以彼此的各种组合来实现。 可选功能包括过程电压 - 温度（“PVT”）变化保护电路，其使增益相对独立于过程，电压和/或温度变化。 可选功能还包括带宽增强电路。

公开(公告)号：US07205840B2

公开(公告)日：2007-04-17

申请号：US11165493

申请日：2005-06-24

申请人： Sandeep Kumar Gupta ,  Venugopal Gopinathan

发明人： Sandeep Kumar Gupta ,  Venugopal Gopinathan

IPC分类号： H03F3/45

CPC分类号： H03F1/52 ,  H03F1/523 ,  H03F3/45085 ,  H03F3/45183 ,  H03F2200/447 ,  H03F2203/45288 ,  H03F2203/45292 ,  H03F2203/45324 ,  H03F2203/45336 ,  H03F2203/45398 ,  H03F2203/45696 ,  H03F2203/45722

摘要： A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

摘要翻译： CMOS增益级包括偏置电路，其配置成在没有源极跟随器电路的情况下确保后续级的饱和。 CMOS增益级可选择用于制造CMOS增益级的工艺技术的电源电压大于允许的电源电压。 为了保护CMOS增益级中的CMOS器件，公开了可选的漏极到体结结穿通保护电路。 各种可选特征可以单独实现和/或以彼此的各种组合来实现。 可选功能包括过程电压 - 温度（“PVT”）变化保护电路，其使增益相对独立于过程，电压和/或温度变化。 可选功能还包括带宽增强电路。

公开(公告)号：US06758516B1

公开(公告)日：2004-07-06

申请号：US10250214

申请日：2003-06-13

申请人： Joseph Edward Abramczyk ,  Karthik Chitoor ,  Paul Culbertson ,  Zheng James Peng ,  Sandeep Kumar Gupta ,  Eric Layton Stratten ,  Herbert Yang

发明人： Joseph Edward Abramczyk ,  Karthik Chitoor ,  Paul Culbertson ,  Zheng James Peng ,  Sandeep Kumar Gupta ,  Eric Layton Stratten ,  Herbert Yang

IPC分类号： B62D2522

CPC分类号： B62D21/157 ,  B62D25/025

摘要： An automobile includes a door, inner and outer rocker panels, and a floor pan joined to the inner rocker panel. A structural frame extends under the body. A frame standoff member is mounted to the inner rocker panel and extends inboard to a frame rail. The frame standoff member is separated from the frame rail by a clearance gap. Once the gap is closed due to lateral deformation of the door, rocker panels, and floor pan, the frame standoff member will resist further deformation of the door and rocker panels without dynamically coupling the door or rocker panels to the frame rail during normal operation of the vehicle.

摘要翻译： 汽车包括门，内外摇臂面板和连接到内摇杆面板的地板。 结构框架在身体下方延伸。 框架支座构件安装到内摇杆面板并且在内侧延伸到框架轨道。 框架支撑构件与框架轨道间隔开间隙。 一旦由于门，摇臂板和地板盘的横向变形而使间隙闭合，框架支撑构件将抵抗门和摇杆面板的进一步变形，而不会在正常操作期间将门或摇杆面板动态地联接到框架轨道 机动车。

公开(公告)号：US12046601B2

公开(公告)日：2024-07-23

申请号：US17684072

申请日：2022-03-01

申请人： Sandeep Kumar Gupta

发明人： Sandeep Kumar Gupta

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L2027/11881

摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i−1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M−1, wherein a sum of all Xj voltages for j=1:(M−1) is greater than 0.25*VDD.

公开(公告)号：US11953963B2

公开(公告)日：2024-04-09

申请号：US17672686

申请日：2022-02-16

申请人： Sandeep Kumar Gupta

发明人： Sandeep Kumar Gupta

IPC分类号： G06F1/32 ,  G06F1/3206

CPC分类号： G06F1/3206

摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M−1.

公开(公告)号：US20230259148A1

公开(公告)日：2023-08-17

申请号：US17672686

申请日：2022-02-16

申请人： Sandeep Kumar Gupta

发明人： Sandeep Kumar Gupta

IPC分类号： G05F1/46

CPC分类号： G05F1/46

摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M−1.

公开(公告)号：US20120284694A1

公开(公告)日：2012-11-08

申请号：US13549147

申请日：2012-07-13

申请人： Lawrence Taylor Waugh ,  Sandeep Kumar Gupta

发明人： Lawrence Taylor Waugh ,  Sandeep Kumar Gupta

IPC分类号： G06F9/44

CPC分类号： G06F8/77 ,  G06F11/3616

摘要： A method and system is described for managing the development of software source code, and in addition, collecting useful metrics about the development process. A first source code is provided in a desired state. The desired state may be the requirement that the source code can be built or the desired state may be the requirement that the source code can be built and pass one or more tests. A second source code is then received. The second source may be a modified copy of the source code. It is then determined whether the second source code is in the desired state, and the first source code is updated using the second source code in response to the second source code being in the desired state. Metrics that may be collected include: the name of a task, time to complete the task, line of code involved, etc.

摘要翻译： 描述了一种用于管理软件源代码开发的方法和系统，此外还收集有关开发过程的有用指标。 以期望的状态提供第一源代码。 期望的状态可以是可以构建源代码的要求，或者期望的状态可以是可以构建源代码并通过一个或多个测试的要求。 然后接收第二个源代码。 第二个源可能是源代码的修改副本。 然后确定第二源代码是否处于期望状态，并且响应于第二源代码处于期望状态，使用第二源代码更新第一源代码。 可能收集的指标包括：任务的名称，完成任务的时间，涉及的代码行等。

公开(公告)号：US07466746B2

公开(公告)日：2008-12-16

申请号：US11148988

申请日：2005-06-09

申请人： Sandeep Kumar Gupta

发明人： Sandeep Kumar Gupta

IPC分类号： H04B1/38

CPC分类号： H03G1/0088 ,  H03F1/26 ,  H04B3/23

摘要： An device and method for a pre-sampling processing is disclosed. The pre-sampling device includes a single amplifier having a virtual ground node, and a feed back circuit connected from an output of the amplifier to the virtual ground node. The feed back circuit includes a plurality of switches connected to the virtual ground node. The switches control a plurality of programmable gain settings. The feed back circuit also includes an adjustable current source that is adjusted according to an estimated echo signal. A current of the adjustable current source is summed at the virtual ground node. The feed back circuit also includes a low pass filter that is tuned to suppress received signal frequencies above a fraction of a sampling frequency of a sampler connected to the pre-sampling device.

摘要翻译： 公开了一种用于预采样处理的装置和方法。 预采样装置包括具有虚拟接地节点的单个放大器和从放大器的输出端连接到虚拟接地节点的反馈电路。 反馈电路包括连接到虚拟接地节点的多个开关。 开关控制多个可编程增益设置。 反馈电路还包括根据估计的回波信号调节的可调电流源。 可调电流源的电流在虚拟接地节点处相加。 反馈电路还包括低通滤波器，该低通滤波器被调谐以将接收到的信号频率抑制在连接到预取样装置的采样器的采样频率的一小部分上。