公开(公告)号：US06821850B2

公开(公告)日：2004-11-23

申请号：US10627917

申请日：2003-07-28

申请人： Sang-Hoan Chang ,  Ki-Seog Kim ,  Keun-Woo Lee ,  Sung-Kee Park

发明人： Sang-Hoan Chang ,  Ki-Seog Kim ,  Keun-Woo Lee ,  Sung-Kee Park

IPC分类号： H02L21336

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/0425 ,  G11C2211/5611

摘要： A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

摘要翻译： 提供多级EEPROM单元及其制造方法，以改善多电平单元的程序特性。 为此，多级闪速EEPROM单元包括浮置栅极，其通过下面的隧道氧化物层与硅衬底电隔离，形成在浮置栅极的顶部上的第一电介质层，形成在第一控制栅极上的第一控制栅极 所述浮置栅极通过所述第一介电层与所述浮置栅极电分离，形成在所述第一控制栅极的侧壁和顶部上的第二介电层，形成在所述第一控制栅极的侧壁和顶部上的第二控制栅极为 通过第二电介质层与第一控制栅极电分离，以及在衬底中形成的与第二控制栅极的两个边缘自对准的源极和漏极。

公开(公告)号：US06630709B2

公开(公告)日：2003-10-07

申请号：US09739401

申请日：2000-12-19

申请人： Sang-Hoan Chang ,  Ki-Seog Kim ,  Keun-Woo Lee ,  Sung-Kee Park

发明人： Sang-Hoan Chang ,  Ki-Seog Kim ,  Keun-Woo Lee ,  Sung-Kee Park

IPC分类号： H01L2976

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/0425 ,  G11C2211/5611

摘要： A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

摘要翻译： 提供多级EEPROM单元及其制造方法，以改善多电平单元的程序特性。 为此，多级闪速EEPROM单元包括浮置栅极，其通过下面的隧道氧化物层与硅衬底电隔离，形成在浮置栅极的顶部上的第一电介质层，形成在第一控制栅极上的第一控制栅极 所述浮置栅极通过所述第一介电层与所述浮置栅极电分离，形成在所述第一控制栅极的侧壁和顶部上的第二介电层，形成在所述第一控制栅极的侧壁和顶部上的第二控制栅极为 通过第二电介质层与第一控制栅极电分离，以及在衬底中形成的与第二控制栅极的两个边缘自对准的源极和漏极。

公开(公告)号：US06697288B2

公开(公告)日：2004-02-24

申请号：US10029283

申请日：2001-12-28

申请人： Ki-Seog Kim ,  Keun-Woo Lee ,  Seoung-Ouk Choi ,  Keon-Soo Shim

发明人： Ki-Seog Kim ,  Keun-Woo Lee ,  Seoung-Ouk Choi ,  Keon-Soo Shim

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C16/24 ,  G11C16/30 ,  Y10T307/766

摘要： A bit line voltage regulation circuit achieves uniform program features and precise cell distribution by providing a high voltage to a bit line regardless of a cell state. For this purpose, the regulation circuit includes a boosting unit for generating the high voltage, a switching unit, connected between the boosting unit and the bit line of a memory cell array, for transferring the high voltage to the bit line and an amplifying unit, for detecting a voltage drop at a detection node on the bit line caused by resistance on the bit line, amplifying the detected voltage drop to produce an amplified voltage driving the switching unit.

摘要翻译： 位线电压调节电路通过向位线提供高电压来实现均匀的程序特征和精确的单元分布，而与单元状态无关。 为此，调节电路包括用于产生高电压的升压单元，连接在升压单元和存储单元阵列的位线之间的用于将高电压传送到位线的放大单元和放大单元， 用于检测由位线上的电阻引起的位线上的检测节点处的电压降，放大检测到的电压降，以产生驱动开关单元的放大电压。