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    Nonvolatile memory device, and its manufacturing method
    1.
    发明申请
    Nonvolatile memory device, and its manufacturing method 有权
    非易失存储器件及其制造方法

    公开(公告)号：US20060114722A1

    公开(公告)日：2006-06-01

    申请号：US11291048

    申请日：2005-11-29

    申请人： Atsushi Yokoi ,  Masao Nakano

    发明人： Atsushi Yokoi ,  Masao Nakano

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C2211/5611 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

    摘要： On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across a gap G1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17, the charges injected depend on the writing voltage applied in control gate layers 21A, 21B and can be localized beneath the control gate layers 21A, 21B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21A, 21B, so that multi-value storage in the memory cell can be realized.

    摘要翻译： 在由一对扩散层13A，13B，第一绝缘层15，电荷累积层17和第二绝缘层19围绕的沟道区域上依次层叠，在第二绝缘层19上， 在间隙G 1间隔开的两个控制栅极层21A，21B设置在沟道宽度方向的中间。 电荷累积层17具有离散的电荷陷阱，因此层中的电荷的移动受到限制。 在电荷累积层17中，注入的电荷取决于施加在控制栅极层21A，21B中的写入电压，并且可以位于施加写入电压的控制栅极层21A，21B的下方。 可以在控制栅极层21A，21B下方的每个电荷累积区域中控制电荷的存在或不存在，从而可以实现存储单元中的多值存储。

    Multi-level flash EEPROM cell and method of manufacture thereof
    3.
    发明申请
    Multi-level flash EEPROM cell and method of manufacture thereof 失效
    多级闪存EEPROM单元及其制造方法

    公开(公告)号：US20040071020A1

    公开(公告)日：2004-04-15

    申请号：US10627917

    申请日：2003-07-28

    申请人： HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. a corporation of Republic of Korea

    发明人： Sang-Hoan Chang ,  Ki-Seog Kim ,  Keun-Woo Lee ,  Sung-Kee Park

    IPC分类号： G11C007/00

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/0425 ,  G11C2211/5611

    摘要： A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

    摘要翻译： 提供多级EEPROM单元及其制造方法，以改善多电平单元的程序特性。 为此，多级闪速EEPROM单元包括浮置栅极，其通过下面的隧道氧化物层与硅衬底电隔离，形成在浮置栅极的顶部上的第一电介质层，形成在第一控制栅极上的第一控制栅极 所述浮置栅极通过所述第一介电层与所述浮置栅极电分离，形成在所述第一控制栅极的侧壁和顶部上的第二介电层，形成在所述第一控制栅极的侧壁和顶部上的第二控制栅极为 通过第二电介质层与第一控制栅极电分离，以及在衬底中形成的与第二控制栅极的两个边缘自对准的源极和漏极。

    Preventing dielectric thickening over a floating gate area of a transistor
    4.
    发明授权
    Preventing dielectric thickening over a floating gate area of a transistor 失效
    防止在晶体管的浮动栅极区域上的电介质增厚

    公开(公告)号：US06630381B1

    公开(公告)日：2003-10-07

    申请号：US09695942

    申请日：2000-10-24

    申请人： Emanuel Hazani

    发明人： Emanuel Hazani

    IPC分类号： H01L218247

    CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/10 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/0403 ,  G11C2029/5002 ,  G11C2211/5611 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5645 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883

    摘要： A process for a memory transistor (e.g. flash-EEPROM cell), which includes forming an isolation-spacer between a control gate and an erase line of over a floating gate by first growing a thin thermal oxide to be in contact with the first sidewall of control gate and thereafter depositing fluorinated-TEOS or tetramethylsilane (TMS) based LPCVD oxide a low temperature of about 250 degrees centigrade. The choice of deposited have lower dielectric constant than that of thermal silicon dioxide which lowers the parasitic capacitance between word lines and erase lines and thereby increases speed performances. The process prevents the formation of a poly-oxide beak under the control gate, thereby the first insulator between the control gate and the floating gate has a uniform thickness. The transistor programs efficiently, is reliable, has low manufacture cost and is physically and electrically down scalable.

    摘要翻译： 一种用于存储晶体管（例如闪速EEPROM单元）的方法，其包括在浮置栅极之间的控制栅极和擦除线之间形成隔离间隔物，首先将薄的热氧化物生长成与第一侧壁接触 然后在大约250摄氏度的低温下沉积氟化TEOS或四甲基硅烷（TMS）的LPCVD氧化物。 沉积的选择具有比热二氧化硅低的介电常数，这降低了字线和擦除线之间的寄生电容，从而增加了速度性能。 该过程防止在控制栅极下形成多晶氧化物喙，由此控制栅极和浮栅之间的第一绝缘体具有均匀的厚度。 晶体管程序有效，可靠，制造成本低，物理和电气可降压。

    Memory with isolatable expandable bit lines
    5.
    发明授权
    Memory with isolatable expandable bit lines 失效
    具有可隔离扩展位线的存储器

    公开(公告)号：US5677867A

    公开(公告)日：1997-10-14

    申请号：US497608

    申请日：1995-06-30

    申请人： Emanuel Hazani

    发明人： Emanuel Hazani

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C13/00

    CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/10 ,  G11C29/50 ,  G11C29/50004 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2029/5002 ,  G11C2211/5611 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5645

    摘要： The invention enables random read and write operations into cells in an array that contains connections from the memory cells that include at least one field effect transistor (FET transistor) to embedded bit line segments which are selectively isolatable and selectively expandable to achieve compactness of number of cell per unit area. In a given segment of the array a first select transistor is connected between a given embedded bit line segment and a first access bit line which functions as a path from a first reference voltage to the drain of a first FET memory transistor set when the first select transistor is turned off, and wherein the first access bit line functions as a path from the source of a second FET memory transistor set to a second reference voltage when the first select transistor is turned on. A second select transistor connected between the embedded bit line segment and a second bit line which functions as a path from said first reference voltage to the drain of a second Memory FET set when the second select transistor is turned off, and wherein said second bit line functions as a path from the source of the first Memory FET set to a second reference voltage when said first select transistor is turned on. The invention also reduces the diffusion isolation spacing between bit-lines by using shield transistors.

    摘要翻译： 本发明使得能够对包含至少一个场效应晶体管（FET晶体管）的存储器单元的连接的阵列中的单元进行随机读和写操作，所述嵌入式位线段被选择性地隔离并选择性地可扩展以实现数量的紧凑 单位面积。 在阵列的给定段中，第一选择晶体管连接在给定的嵌入式位线段和第一存取位线之间，第一存取位线用作从第一参考电压到第一FET存储晶体管组的漏极的路径，当第一选择 晶体管截止，并且其中当第一选择晶体管导通时，第一存取位线用作从第二FET存储晶体管的源极到第二参考电压的路径。 连接在所述嵌入式位线段和第二位线之间的第二选择晶体管，当所述第二选择晶体管截止时，所述第二位线用作从所述第一参考电压到第二存储FET集合的漏极的路径，并且其中所述第二位线 当所述第一选择晶体管导通时，作为从第一存储FET集合的源极到第二参考电压的路径。 本发明还通过使用屏蔽晶体管来减少位线之间的扩散隔离间隔。

    Method of manufacturing a multi-level flash EEPROM cell
    6.
    发明授权
    Method of manufacturing a multi-level flash EEPROM cell 失效
    制造多级闪存EEPROM单元的方法

    公开(公告)号：US06821850B2

    公开(公告)日：2004-11-23

    申请号：US10627917

    申请日：2003-07-28

    申请人： Sang-Hoan Chang ,  Ki-Seog Kim ,  Keun-Woo Lee ,  Sung-Kee Park

    发明人： Sang-Hoan Chang ,  Ki-Seog Kim ,  Keun-Woo Lee ,  Sung-Kee Park

    IPC分类号： H02L21336

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/0425 ,  G11C2211/5611

    摘要： A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

    摘要翻译： 提供多级EEPROM单元及其制造方法，以改善多电平单元的程序特性。 为此，多级闪速EEPROM单元包括浮置栅极，其通过下面的隧道氧化物层与硅衬底电隔离，形成在浮置栅极的顶部上的第一电介质层，形成在第一控制栅极上的第一控制栅极 所述浮置栅极通过所述第一介电层与所述浮置栅极电分离，形成在所述第一控制栅极的侧壁和顶部上的第二介电层，形成在所述第一控制栅极的侧壁和顶部上的第二控制栅极为 通过第二电介质层与第一控制栅极电分离，以及在衬底中形成的与第二控制栅极的两个边缘自对准的源极和漏极。

    Multigate semiconductor device with vertical channel current and method of fabrication
    8.
    发明申请
    Multigate semiconductor device with vertical channel current and method of fabrication 失效
    具有垂直沟道电流的半导体器件和制造方法

    公开(公告)号：US20030139011A1

    公开(公告)日：2003-07-24

    申请号：US10254878

    申请日：2002-09-26

    申请人： Matrix Semiconductor, Inc.

    发明人： James M. Cleeves ,  Vivek Subramanian

    IPC分类号： H01L021/336 ,  H01L021/3205 ,  H01L029/768

    CPC分类号： H01L27/11568 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/5611 ,  G11C2211/5612 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

    摘要： The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface. According to the second aspect of the present invention, a transistor is provided that has a source, a channel, a drain, and a plurality of gates where the channel current flows vertically between the source and drain. According to a third embodiment of the present invention, a memory element is formed using a transistor that has a read current that flows in a direction perpendicular to a substrate in or over which the transistors form. The transistor has a charge storage medium for storing its state. Multiple control gates address the transistor.

    摘要翻译： 本发明是一种多位非易失性存储器及其制造方法。 根据本发明，形成具有第一和第二通道表面的硅通道体。 在第一通道表面附近形成电荷存储介质，并且在第二通道表面附近形成第二电荷存储介质。 与第一通道表面相邻的第一电荷存储介质相邻地形成第一控制栅极，并且邻近第二表面邻近第二电荷存储介质形成第二控制栅极。 根据本发明的第二方面，提供一种具有源极，沟道，漏极和多个栅极的晶体管，其中沟道电流在源极和漏极之间垂直流动。 根据本发明的第三实施例，使用晶体管形成存储元件，该晶体管具有在垂直于晶体管形成的晶体管或其上的衬底的方向上流动的读取电流。 晶体管具有用于存储其状态的电荷存储介质。 多个控制门寻址晶体管。

    Nonvolatile memory device
    10.
    发明授权
    Nonvolatile memory device 失效
    非易失性存储器件

    公开(公告)号：US5859454A

    公开(公告)日：1999-01-12

    申请号：US852022

    申请日：1997-05-06

    申请人： Woong Lim Choi ,  Kyeong Man Ra

    发明人： Woong Lim Choi ,  Kyeong Man Ra

    IPC分类号： G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

    CPC分类号： G11C16/3481 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/3468 ,  H01L27/115 ,  H01L29/42324 ,  G11C2211/5611 ,  G11C2211/5621 ,  G11C2211/5624

    摘要： A nonvolatile memory device includes a floating gate for storing a charge carrier during programming, a program gate coupled to the floating gate and performing programming by injecting the charge carrier induced from the outside during programming into the floating gate, an erasure gate coupled to the floating gate and emitting the charge carrier stored in the floating gate to the outside during erasure to outside, a control gate coupled to the floating gate and controlling an amount of the charge carrier provided from the program gate to the floating gate during programming, and a transistor coupled to the floating gate and verifying the amount of the charge carrier provided form the program gate during programming, the transistor including a channel region and source and drain regions.

    摘要翻译： 非易失性存储器件包括用于在编程期间存储电荷载体的浮动栅极，耦合到浮置栅极的编程栅极，并且在编程期间将从外部感应的电荷载流子注入到浮置栅极中执行编程;耦合到浮置栅极的擦除栅极 栅极，并且在擦除期间将存储在浮动栅极中的电荷载流子发射到外部;控制栅极，耦合到浮置栅极，并且在编程期间控制从编程门到浮置栅极提供的电荷载流子的量;以及晶体管 耦合到浮置栅极并且在编程期间验证从编程门提供的电荷载流子的量，所述晶体管包括沟道区域和源极和漏极区域。