公开(公告)号：US20120049266A1

公开(公告)日：2012-03-01

申请号：US13216004

申请日：2011-08-23

申请人： Sang-Woo OH ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

发明人： Sang-Woo OH ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

IPC分类号： H01L29/788 ,  H01L21/283

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

摘要： A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

摘要翻译： 一种半导体器件，包括其中形成有沟槽的衬底，多个栅极结构，隔离层图案和绝缘层间图案。 衬底包括由沟槽限定的多个有源区，并在第二方向彼此间隔开。 每个有源区域沿着基本上垂直于第二方向的第一方向延伸。 多个栅极结构中的每一个包括依次层叠在基板上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 隔离层图案形成在沟槽中。 第一隔离层图案在至少一对相邻的浮置栅极的侧壁之间具有至少一个第一气隙。 绝缘层间图案形成在栅极结构之间，第一绝缘层间图案沿第二方向延伸。

公开(公告)号：US09035419B2

公开(公告)日：2015-05-19

申请号：US13216004

申请日：2011-08-23

申请人： Sang-Woo Oh ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

发明人： Sang-Woo Oh ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

IPC分类号： H01L21/764 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

摘要： A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

摘要翻译： 一种半导体器件，包括其中形成有沟槽的衬底，多个栅极结构，隔离层图案和绝缘层间图案。 衬底包括由沟槽限定的多个有源区，并在第二方向彼此间隔开。 每个有源区域沿着基本上垂直于第二方向的第一方向延伸。 多个栅极结构中的每一个包括依次层叠在基板上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 隔离层图案形成在沟槽中。 第一隔离层图案在至少一对相邻的浮置栅极的侧壁之间具有至少一个第一气隙。 绝缘层间图案形成在栅极结构之间，第一绝缘层间图案沿第二方向延伸。

公开(公告)号：US20120223379A1

公开(公告)日：2012-09-06

申请号：US13407187

申请日：2012-02-28

申请人： Hyun-Sil OH ,  Sung-Hoi Hur ,  Dae-Sin Kim

发明人： Hyun-Sil OH ,  Sung-Hoi Hur ,  Dae-Sin Kim

IPC分类号： H01L27/105 ,  H01L21/762

CPC分类号： H01L27/11521 ,  G11C16/0466

摘要： A non-volatile memory device includes a substrate including a plurality of active regions and a plurality of device isolating trenches formed between a respective one of each of the active regions along a first direction in the substrate. A plurality of gate structures each including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode is formed on the substrate. A first insulating layer pattern is provided within the device isolating trenches. A second insulating layer pattern is formed along an inner surface portion of a gap between the gate structures. An impurity doped polysilicon pattern is formed on the second insulating layer pattern in the gap between the gate structures.

摘要翻译： 非易失性存储器件包括：衬底，其包括多个有源区和多个器件隔离沟槽，沿着衬底中的第一方向形成在每个有源区中的相应一个之间。 在衬底上形成各自包括隧道绝缘层图案，浮栅电极，电介质层图案和控制栅极电极的多个栅极结构。 在器件隔离沟槽内提供第一绝缘层图案。 沿着栅极结构之间的间隙的内表面部分形成第二绝缘层图案。 在栅极结构之间的间隙中的第二绝缘层图案上形成杂质掺杂多晶硅图案。

公开(公告)号：US20150115345A1

公开(公告)日：2015-04-30

申请号：US14519285

申请日：2014-10-21

申请人： Etienne Nowak ,  Dae-Sin Kim ,  Hye-Young Kwon ,  Jae-Ho Kim ,  Jin-Woo Park ,  Ji-Woong Sue

发明人： Etienne Nowak ,  Dae-Sin Kim ,  Hye-Young Kwon ,  Jae-Ho Kim ,  Jin-Woo Park ,  Ji-Woong Sue

IPC分类号： H01L27/115 ,  H01L21/31

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A vertical memory device includes a channel, a conductive pattern, gate electrodes, a bit line and a conductive line. A plurality of the channels and the conductive patterns extend in a vertical direction from a top surface of a substrate. The gate electrodes surround outer sidewalls of the channels and the conductive patterns. The gate electrodes are stacked in the vertical direction to be spaced apart from each other. The bit line is electrically connected to the channels. The conductive line is electrically connected to the conductive patterns.

摘要翻译： 垂直存储器件包括通道，导电图案，栅电极，位线和导线。 多个通道和导电图案从衬底的顶表面沿垂直方向延伸。 栅电极围绕通道的外侧壁和导电图案。 栅电极在垂直方向上堆叠以彼此间隔开。 位线电连接到通道。 导线与导电图形电连接。

公开(公告)号：US08627257B2

公开(公告)日：2014-01-07

申请号：US13570498

申请日：2012-08-09

申请人： Jae-Ho Kim ,  Dae-Sin Kim ,  Hyun-Jae Kim ,  Young-Gu Kim

发明人： Jae-Ho Kim ,  Dae-Sin Kim ,  Hyun-Jae Kim ,  Young-Gu Kim

IPC分类号： G06F17/50

CPC分类号： G06F12/0246 ,  G06F2212/7206

摘要： In a computer-implemented method of designing a nonvolatile memory device, first parameters associated with external environmental conditions are set. Second parameters associated with structural characteristics and internal environmental conditions are set. A first initial operation condition associated with an erase operation is determined based on the first and second parameters. A second initial operation condition associated with a program operation is determined based on the first and second parameters and the first initial operation condition. A final operation condition associated with reliability is determined based on the first and second parameters, and the first and second initial operation condition.

摘要翻译： 在设计非易失性存储器件的计算机实现方法中，设置与外部环境条件相关联的第一参数。 设定与结构特征和内部环境条件相关的第二参数。 基于第一和第二参数确定与擦除操作相关联的第一初始操作条件。 基于第一和第二参数和第一初始操作条件来确定与程序操作相关联的第二初始操作条件。 基于第一和第二参数以及第一和第二初始操作条件来确定与可靠性相关联的最终操作条件。