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    Semiconductor devices including an air-gap and methods of manufacturing the same
    1.
    发明授权
    Semiconductor devices including an air-gap and methods of manufacturing the same 有权
    包括气隙的半导体器件及其制造方法

    公开(公告)号：US09035419B2

    公开(公告)日：2015-05-19

    申请号：US13216004

    申请日：2011-08-23

    申请人： Sang-Woo Oh ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

    发明人： Sang-Woo Oh ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

    IPC分类号： H01L21/764 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/788

    CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

    摘要： A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

    摘要翻译： 一种半导体器件，包括其中形成有沟槽的衬底，多个栅极结构，隔离层图案和绝缘层间图案。 衬底包括由沟槽限定的多个有源区，并在第二方向彼此间隔开。 每个有源区域沿着基本上垂直于第二方向的第一方向延伸。 多个栅极结构中的每一个包括依次层叠在基板上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 隔离层图案形成在沟槽中。 第一隔离层图案在至少一对相邻的浮置栅极的侧壁之间具有至少一个第一气隙。 绝缘层间图案形成在栅极结构之间，第一绝缘层间图案沿第二方向延伸。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120049266A1

    公开(公告)日：2012-03-01

    申请号：US13216004

    申请日：2011-08-23

    申请人： Sang-Woo OH ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

    发明人： Sang-Woo OH ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

    IPC分类号： H01L29/788 ,  H01L21/283

    CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

    摘要： A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

    摘要翻译： 一种半导体器件，包括其中形成有沟槽的衬底，多个栅极结构，隔离层图案和绝缘层间图案。 衬底包括由沟槽限定的多个有源区，并在第二方向彼此间隔开。 每个有源区域沿着基本上垂直于第二方向的第一方向延伸。 多个栅极结构中的每一个包括依次层叠在基板上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 隔离层图案形成在沟槽中。 第一隔离层图案在至少一对相邻的浮置栅极的侧壁之间具有至少一个第一气隙。 绝缘层间图案形成在栅极结构之间，第一绝缘层间图案沿第二方向延伸。

    Transistor and novolatile memory device including the same
    3.
    发明申请
    Transistor and novolatile memory device including the same 审中-公开
    晶体管和不挥发性存储器件包括它们

    公开(公告)号：US20070181949A1

    公开(公告)日：2007-08-09

    申请号：US11649368

    申请日：2007-01-04

    申请人： Jung-Dal Choi ,  Sang-Hun Jeon ,  Young-Kwan Park ,  Keun-Ho Lee

    发明人： Jung-Dal Choi ,  Sang-Hun Jeon ,  Young-Kwan Park ,  Keun-Ho Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115

    摘要： A transistor includes a gate electrode on a substrate, source/drain regions in the substrate at both sides of the gate electrode, and a channel region defined between the source/drain regions, wherein the channel region includes a recessed region and at least one of the source/drain regions is spaced away from the recessed region of the channel region.

    摘要翻译： 晶体管包括衬底上的栅电极，位于栅电极两侧的衬底中的源/漏区和限定在源/漏区之间的沟道区，其中沟道区包括凹陷区和至少之一 源极/漏极区域与沟道区域的凹陷区域间隔开。

    Simulation method of wafer warpage
    4.
    发明申请
    Simulation method of wafer warpage 审中-公开
    晶圆翘曲的仿真方法

    公开(公告)号：US20070087529A1

    公开(公告)日：2007-04-19

    申请号：US11580352

    申请日：2006-10-13

    申请人： Won-Young Chung ,  Tai-Kyung Kim ,  Young-Kwan Park ,  Ui-Hui Kwon ,  Kyu-Baik Chang

    发明人： Won-Young Chung ,  Tai-Kyung Kim ,  Young-Kwan Park ,  Ui-Hui Kwon ,  Kyu-Baik Chang

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L21/76838

    摘要： Disclosed is a simulation method for determining wafer warpage. This method includes dividing layers and evaluating a composition ratio of materials composing the layers. The method mathematically transforms a semiconductor device, which is constructed as a complicated structure with various materials, into a simplified, mathematically equivalent stacked structure comprising a plurality of unit layer, and utilizes values of mechanical characteristics, which are obtained from the transformed layer structure, for estimating wafer warpage. As a result, it is possible to complete an operation of wafer warpage simulation using information about pattern density of the semiconductor device.

    摘要翻译： 公开了一种用于确定晶片翘曲的模拟方法。 该方法包括分层和评估构成层的材料的组成比。 该方法将构成为具有各种材料的复杂结构的半导体器件数学地变换为包括多个单位层的简化的，数学上等效的堆叠结构，并利用从变换层结构获得的机械特性值， 用于估计晶片翘曲。 结果，可以使用关于半导体器件的图案密度的信息来完成晶片翘曲模拟的操作。