公开(公告)号：US09780096B2

公开(公告)日：2017-10-03

申请号：US14965532

申请日：2015-12-10

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L23/528 ,  H01L29/423 ,  H01L29/792 ,  H01L27/108 ,  H01L23/31 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/78 ,  H01L27/1157 ,  H01L27/11575

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20160204111A1

公开(公告)日：2016-07-14

申请号：US14965532

申请日：2015-12-10

申请人： Sang-Yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-Yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L23/31 ,  H01L23/528 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

摘要翻译： 垂直存储器件及其制造方法包括提供包括电池阵列区域和外围电路区域的衬底，在电池阵列区域中形成模具结构，形成通过模具结构的共同源极线的开口，以及 在垂直于衬底的顶表面的第一方向上延伸，形成第一接触插塞，该第一接触插塞具有限定用于公共源极线的开口中的凹陷区域的内侧壁，以及形成与内侧壁电连接的公共源位线接触 的第一个接触插头。

公开(公告)号：US10811421B2

公开(公告)日：2020-10-20

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L27/1157 ,  H01L27/11575 ,  H01L23/31 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20180026041A1

公开(公告)日：2018-01-25

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/792 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/1157 ,  H01L23/31 ,  H01L27/11582

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.