摘要:
A burn-in stress circuit for a semiconductor memory device. A burn-in enable signal generator generates a burn-in enable signal in response to a plurality of control signals. A wordline predecoder generates a wordline driving voltage for driving a wordline in response to the burn-in enable signal and another a plurality of control signals. A wordline decoder applies the wordline driving voltage to the wordline in response to the burn-in enable signal and another plurality of control signals. To reduce the stress testing time by stressing multiple rows of a memory array simultaneously, all of the wordlines (rows) are stressed and or tested at the same time. To select all of the wordlines, the wordlines are selected sequentially, but each selected wordline is held in a selected state by a latching mechanism while all of the other wordlines are being selected as well. When all of the wordlines (or a desired subset) have been selected, the burn-in stress test begins.
摘要:
Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.
摘要:
Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.
摘要:
Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.
摘要:
Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.