公开(公告)号：US06745318B1

公开(公告)日：2004-06-01

申请号：US09376830

申请日：1999-08-18

申请人： Sanjay Mansingh ,  Niteen Patkar ,  Korbin Van Dyke ,  Stephen Hale ,  Dee Tovey ,  Nital Patwa ,  Stephen C. Purcell

发明人： Sanjay Mansingh ,  Niteen Patkar ,  Korbin Van Dyke ,  Stephen Hale ,  Dee Tovey ,  Nital Patwa ,  Stephen C. Purcell

IPC分类号： G06F1710

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3897

摘要： An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. The dynamic arithmetic logic unit receives the decoded instruction and configures at least one configurable arithmetic logic unit to perform an operation contained within the decoded instruction.

摘要翻译： 提供可配置处理的装置包括取出模块，解码器和动态运算单元。 提取模块可操作以获取至少一个指令并将其提供给解码器。 解码器接收指令并对其进行解码。 动态算术逻辑单元接收解码指令，并配置至少一个可配置的算术逻辑单元，以执行解码指令中包含的操作。

公开(公告)号：US06651159B1

公开(公告)日：2003-11-18

申请号：US09449956

申请日：1999-11-29

申请人： Tiruvur R. Ramesh ,  Sanjay Mansingh ,  Korbin Van Dyke

发明人： Tiruvur R. Ramesh ,  Sanjay Mansingh ,  Korbin Van Dyke

IPC分类号： G06F9455

CPC分类号： G06F9/45533 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/30174

摘要： A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.

摘要翻译： 用于处理器的浮点寄存器堆栈组合多个两个通用寄存器以形成用于x86指令的寄存器堆栈，并留下剩余的通用寄存器用于处理器的本机指令。 通过将x86源映射到x86堆栈中的两个通用寄存器堆栈和操作x86指令，处理器的寄存器堆栈能够支持处理器的本地指令集和x86指令集，而不增加寄存器堆栈的大小 。

公开(公告)号：US20110314189A1

公开(公告)日：2011-12-22

申请号：US13222531

申请日：2011-08-31

申请人： Sanjay Mansingh

发明人： Sanjay Mansingh

IPC分类号： G06F5/00

CPC分类号： G06F13/385

摘要： A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.

公开(公告)号：US08078800B2

公开(公告)日：2011-12-13

申请号：US12479063

申请日：2009-06-05

申请人： Maziar H. Moallem ,  Sanjay Mansingh ,  Richard F. Avra

发明人： Maziar H. Moallem ,  Sanjay Mansingh ,  Richard F. Avra

IPC分类号： G06F12/00

CPC分类号： G06F1/3203

摘要： In one embodiment, an integrated circuit includes a processor, an internal memory, and a memory controller coupled to an external memory. The integrated circuit may support two or more modes of operation, with different operating points. To switch from one operating point to another, code executed by the processor may copy switch code from the external memory into the internal memory, and may jump to the switch code. Executing out of the internal memory, the switch code may communicate with the memory controller to cause the external memory to enter into self-refresh mode. The operating point may be altered, and the switch code may reinitialize the memory controller after the integrated circuit has stabilized at the new operating point. After the memory controller's physical interface circuit has relocked, the external memory may exit self-refresh mode.

摘要翻译： 在一个实施例中，集成电路包括处理器，内部存储器和耦合到外部存储器的存储器控​​制器。 集成电路可以支持具有不同操作点的两种或更多种操作模式。 要从一个工作点切换到另一个工作点，由处理器执行的代码可将外部存储器中的开关代码复制到内部存储器中，并可跳转到开关代码。 从内部存储器执行，开关代码可以与存储器控制器通信，以使外部存储器进入自刷新模式。 工作点可能会发生变化，并且开关代码可能会在集成电路稳定在新的工作点之后重新初始化存储器控制器。 在内存控制器的物理接口电路重新锁定后，外部存储器可能会退出自刷新模式。

公开(公告)号：US07228404B1

公开(公告)日：2007-06-05

申请号：US09672440

申请日：2000-09-28

申请人： Ronak Patel ,  Korbin S. Van Dyke ,  T.R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Sanjay Mansingh ,  Paul William Campbell

发明人： Ronak Patel ,  Korbin S. Van Dyke ,  T.R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Sanjay Mansingh ,  Paul William Campbell

IPC分类号： G06F9/00

CPC分类号： G06F9/30174 ,  G06F9/3851 ,  G06F9/3861

摘要： A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. Instruction execution is monitored for a condition that is a superset of a condition whose occurrence is desired to be detected, and a first exception is raised as a result of recognizing the superset condition. Software filters the superset condition to determine whether the monitored condition has occurred, and if so, the software establishes a second exception to be raised after execution of further instructions of the instruction stream. When it is recognized that an instruction is to affect the execution of a second instruction, the processor is set into single-step mode. After the second instruction is executed, the computer is set out of single-step mode.

摘要翻译： 一台电脑。 当识别到在建筑上可见的存储位置中要求建筑上可见的副作用的指令时，存储代表该副作用的结构可视表示的值，代表值的格式不同于体系结构 副作用的隐形表示。 恢复执行，而不产生架构上可见的副作用。 之后，对应于代表值的架构可视化表示被写入架构可见的存储位置。 在上下文切换中，写入第一进程的上下文并加载第二进程的上下文以使第二进程执行。 至少一些指令在上下文资源集合之外保持存储资源的结果，并且标记指令以指示是否可以在标记指令的边界执行上下文切换。 监视指示执行是作为期望发生的条件的超集的条件，并且作为识别超集条件的结果而引起第一异常。 软件过滤超集条件以确定监视条件是否已经发生，如果是，则软件在执行指令流的进一步指令之后建立第二个异常。 当识别到指令影响第二指令的执行时，处理器被设置为单步模式。 执行第二条指令后，计算机将处于单步模式。

公开(公告)号：US08032673B2

公开(公告)日：2011-10-04

申请号：US12637338

申请日：2009-12-14

申请人： Sanjay Mansingh

发明人： Sanjay Mansingh

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/385

摘要： A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactons sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.

摘要翻译： PIO交易单元包括输入缓冲器，响应缓冲器和控制单元。 输入缓冲器可以接收并存储由一个或多个transactons源发送的PIO写入操作。 每个PIO写操作可以包括标识事务源的源标识符。 响应缓冲器可以存储对应于要发送到由标识符标识的事务源的各个PIO写入操作的响应操作。 在从输入缓冲器发送给定的PIO写入操作之前，控制单元可以将对应于给定PIO写入操作的特定响应操作存储在响应缓冲器中。 如果给定的PIO写入操作是可缓冲的并且不存在具有存储在输入缓冲器中的相同源标识符的不可缓冲PIO写入操作，则控制单元可以将特定响应操作存储在响应缓冲器内。

公开(公告)号：US06205461B1

公开(公告)日：2001-03-20

申请号：US09157090

申请日：1998-09-18

申请人： Sanjay Mansingh

发明人： Sanjay Mansingh

IPC分类号： G06F738

CPC分类号： G06F7/485 ,  G06F7/49915 ,  G06F7/49936 ,  G06F7/49957

摘要： A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit selects a result as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas and the presence of a guard bit. The result selected by the fast rounding unit is received by a leading zero count unit, which counts the leading zeros of the result. A second slower rounding unit meanwhile makes a selection between the incremented, unincremented, and complemented results based on the rounding mode, the sign of the result and whether the result is exact. The result is inexact when both the most significant bit and the guard bit are equal to one. While the slower rounding unit may take longer to determine the appropriate selection, the result selected is the most accurate. Based on the number of leading zeros determined from the result selected by the fast rounding unit, the bits in the result selected by the slower rounding unit are left shifted thereby normalizing the result.

摘要翻译： 浮点运算逻辑单元包括两个舍入单元，它们在进位传播加法器的递增，非增加和补码结果之间进行选择。 快速舍入单元基于操作数的指数的相等或不等式，尾数的相对大小和保护位的存在，将结果选择为近似。 由快速舍入单元选择的结果由前导零计数单元接收，该计数单元计算结果的前导零。 第二个较慢的舍入单位同时根据舍入模式，结果的符号以及结果是否精确地在递增的，未增加的和补充的结果之间进行选择。 当最高有效位和保护位都等于1时，结果不准确。 虽然较慢的舍入单位可能需要较长时间来确定适当的选择，但所选的结果是最准确的。 根据从快速舍入单元选择的结果确定的前导零的数量，通过较慢舍入单元选择的结果中的位左移，从而使结果标准化。

公开(公告)号：US08645743B2

公开(公告)日：2014-02-04

申请号：US12951788

申请日：2010-11-22

申请人： Erik P. Machnicki ,  Hao Chen ,  Sanjay Mansingh

发明人： Erik P. Machnicki ,  Hao Chen ,  Sanjay Mansingh

IPC分类号： G06F1/00

CPC分类号： H03L7/07 ,  H03L7/0814

摘要： An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

摘要翻译： 在频率变化期间，有效的延迟锁定环（DLL）训练协议包括具有包含主DLL和从属DLL的存储器物理层（PHY）单元的集成电路。 主DLL可以将第一参考时钟延迟一定量，并提供对应于延迟量的参考延迟值。 从属DLL可以基于接收的配置延迟值将第二参考时钟延迟第二量。 接口单元可以基于参考延迟值生成配置延迟值。 功率管理单元可以提供第二参考时钟的频率正在改变的指示。 响应于接收到指示，接口单元可以使用预定的缩放值来生成对应于新频率的新的配置延迟值，并向存储器PHY单元提供新的配置延迟值。

公开(公告)号：US06199090B1

公开(公告)日：2001-03-06

申请号：US09100499

申请日：1998-06-19

申请人： Sanjay Mansingh ,  Stephen Clark Purcell

发明人： Sanjay Mansingh ,  Stephen Clark Purcell

IPC分类号： G06F750

CPC分类号： G06F7/506

摘要： A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight (“first weight”). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight (“second weight”) one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.

摘要翻译： 双增量加法器包括：与门，其被配置为接收公共权重（“第一权重”）的两个输入值的位。 与门具有被配置为携带“与”位的输出端子。 三输入XOR门被配置为接收比第一权重更有一位的公共权重（“第二权重”）的两个输入值的位。 三个输入XOR门被配置为将这些值与“和”位进行异或运算，以产生三输入异或位。

公开(公告)号：US08327044B2

公开(公告)日：2012-12-04

申请号：US13222531

申请日：2011-08-31

申请人： Sanjay Mansingh

发明人： Sanjay Mansingh

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/385

摘要： A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.

摘要翻译： PIO交易单元包括输入缓冲器，响应缓冲器和控制单元。 输入缓冲器可以接收和存储由一个或多个事务源发送的PIO写入操作。 每个PIO写操作可以包括标识事务源的源标识符。 响应缓冲器可以存储对应于要发送到由源标识符标识的事务源的各个PIO写入操作的响应操作。 在从输入缓冲器发送给定的PIO写入操作之前，控制单元可以将对应于给定PIO写入操作的特定响应操作存储在响应缓冲器中。 如果给定的PIO写入操作是可缓冲的并且不存在具有存储在输入缓冲器中的相同源标识符的不可缓冲PIO写入操作，则控制单元可以将特定响应操作存储在响应缓冲器内。