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    Floating point register stack management for CISC
    1.
    发明授权
    Floating point register stack management for CISC 有权
    CISC浮点寄存器堆栈管理

    公开(公告)号：US06651159B1

    公开(公告)日：2003-11-18

    申请号：US09449956

    申请日：1999-11-29

    申请人： Tiruvur R. Ramesh ,  Sanjay Mansingh ,  Korbin Van Dyke

    发明人： Tiruvur R. Ramesh ,  Sanjay Mansingh ,  Korbin Van Dyke

    IPC分类号： G06F9455

    CPC分类号： G06F9/45533 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/30174

    摘要： A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.

    摘要翻译： 用于处理器的浮点寄存器堆栈组合多个两个通用寄存器以形成用于x86指令的寄存器堆栈，并留下剩余的通用寄存器用于处理器的本机指令。 通过将x86源映射到x86堆栈中的两个通用寄存器堆栈和操作x86指令，处理器的寄存器堆栈能够支持处理器的本地指令集和x86指令集，而不增加寄存器堆栈的大小 。

    Variable-length code decoder
    3.
    发明授权
    Variable-length code decoder 有权
    可变长度码解码器

    公开(公告)号：US08824819B2

    公开(公告)日：2014-09-02

    申请号：US13305084

    申请日：2011-11-28

    申请人： Chad E. Fogg ,  Nital P. Patwa ,  Parin B. Dalal ,  Stephen C. Purcell ,  Korbin Van Dyke ,  Stephen C. Hale

    发明人： Chad E. Fogg ,  Nital P. Patwa ,  Parin B. Dalal ,  Stephen C. Purcell ,  Korbin Van Dyke ,  Stephen C. Hale

    IPC分类号： G06K9/36 ,  G06K9/46

    CPC分类号： H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N19/91

    摘要： An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

    摘要翻译： 一种装置包括至少一个通用寄存器和至少一个专用寄存器和执行单元，其并行地执行至少两个指令，以解码可变长度代码，其中每个指令共享至少一个通用寄存器的使用 和至少一个专用寄存器。 在一个示例中，处理器在多个通用寄存器之间存储可变长度代码信息，并通过解码至少一个可变长度代码来生成解码的可变长度代码信息。 处理器还在多个通用寄存器之间存储解码的可变长度代码信息。

    Transferring execution from one instruction stream to another
    4.
    发明申请
    Transferring execution from one instruction stream to another 有权
    将执行从一个指令流传输到另一个指令流

    公开(公告)号：US20050086650A1

    公开(公告)日：2005-04-21

    申请号：US11003768

    申请日：2004-12-02

    申请人： John Yates ,  David Reese ,  Paul Hohensee ,  Stephen Purcell ,  Korbin Van Dyke

    发明人： John Yates ,  David Reese ,  Paul Hohensee ,  Stephen Purcell ,  Korbin Van Dyke

    IPC分类号： G06F9/455 ,  G06F9/45 ,  G06F7/38 ,  G06F9/44 ,  G06F15/00 ,  G06F15/76

    CPC分类号： G06F9/45533

    摘要： A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

    摘要翻译： 计算机具有能够执行两个指令集架构（ISA）的指令流水线电路。 二进制翻译器至少将计算机程序的选定部分从ISA的较低性能转换为ISA的更高性能的一个。 当即将执行在低性能ISA中编码的程序区域时，硬件启动查询，以确定是否存在更高性能的转换。 如果是这样，即将执行的指令被中止，并且控制转移到更高性能的转换。 执行较高性能的翻译后，在排除后的指令下游的一个点重新建立较低性能区域的执行，在逻辑上相当于在较低性能区域的代码被允许的情况下 继续。

    Variable-length code decoder
    6.
    发明授权
    Variable-length code decoder 有权
    可变长度码解码器

    公开(公告)号：US08086055B2

    公开(公告)日：2011-12-27

    申请号：US12428045

    申请日：2009-04-22

    申请人： Chad E. Fogg ,  Nital P. Patwa ,  Parin B. Dalal ,  Stephen C. Purcell ,  Korbin Van Dyke ,  Steve C. Hale

    发明人： Chad E. Fogg ,  Nital P. Patwa ,  Parin B. Dalal ,  Stephen C. Purcell ,  Korbin Van Dyke ,  Steve C. Hale

    IPC分类号： G06K9/36 ,  G06K9/46

    CPC分类号： H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N19/91

    摘要： An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

    摘要翻译： 一种装置包括至少一个通用寄存器和至少一个专用寄存器和执行单元，其并行地执行至少两个指令，以解码可变长度代码，其中每个指令共享至少一个通用寄存器的使用 和至少一个专用寄存器。 在一个示例中，处理器在多个通用寄存器之间存储可变长度代码信息，并通过解码至少一个可变长度代码来生成解码的可变长度代码信息。 处理器还在多个通用寄存器之间存储解码的可变长度代码信息。

    Method of integrating a personal computing system and apparatus thereof
    9.
    发明授权
    Method of integrating a personal computing system and apparatus thereof 有权
    集成个人计算系统及其装置的方法

    公开(公告)号：US07769988B1

    公开(公告)日：2010-08-03

    申请号：US09471877

    申请日：1999-12-23

    申请人： Adrian Sfarti ,  Korbin Van Dyke ,  Michael Frank ,  Arkadi Avrukin

    发明人： Adrian Sfarti ,  Korbin Van Dyke ,  Michael Frank ,  Arkadi Avrukin

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F13/4027 ,  G06F2213/0038 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method of integrating a personal computing system and apparatus thereof include processing that begins by integrating a central processing unit with a North bridge on a single substrate such that the central processing unit is directly coupled to the North bridge via an internal bus. The processing then continues by providing memory access requests from the central processing unit to the North bridge at a rate of the central processing unit. The processing continues by having the North bridge buffer the memory access request and subsequently process the memory access requests at a rate of the memory. The method may be expanded by integrating a South bridge onto the same substrate as well as integrating system memory onto the same substrate.

    摘要翻译： 集成个人计算系统及其装置的方法包括通过将中央处理单元与单个基板上的北桥集成开始的处理，使得中央处理单元经由内部总线直接耦合到北桥。 然后通过以中央处理单元的速率从中央处理单元向北桥提供存储器访问请求来继续处理。 通过使北桥缓冲存储器访问请求并随后以存储器的速率处理存储器访问请求，继续处理。 可以通过将南桥集成到相同的衬底上并将系统存储器集成到相同的衬底上来扩展该方法。

    Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
    10.
    发明授权
    Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency 失效
    用于存储到指令流检测和维持分支预测高速缓存一致性的方法和装置

    公开(公告)号：US5649137A

    公开(公告)日：1997-07-15

    申请号：US582294

    申请日：1996-01-03

    申请人： John G. Favor ,  Korbin Van Dyke ,  David R. Stiles

    发明人： John G. Favor ,  Korbin Van Dyke ,  David R. Stiles

    IPC分类号： G06F9/38 ,  G06F9/42

    CPC分类号： G06F9/3812 ,  G06F9/3844

    摘要： The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache. Upon such a detection, that entry in the instruction cache is invalidated, and the corresponding entry in the branch prediction cache is invalidated. A subsequent attempt to use an instruction in the branch prediction cache which has been invalidated will detect that it is not valid, and will instead go to main memory to fetch the instruction, where it has been modified.

    摘要翻译： 本发明提供了当执行的指令尝试改变这样的指令（“存储到指令流”）时更新分支预测高速缓存中的两个指令和最近提供给来自高速缓存的指令流水线的指令。 分支预测高速缓存（BPC）包括识别导致分支的指令的地址的标签，在每个分支指令的最后出现时被分支的目标地址的记录以及从该目标开始的前几个指令的副本 地址。 提供单独的指令高速缓存用于指令的正常执行，并且从系统总线写入分支预测高速缓存的所有指令也必须存储在指令高速缓存中。 指令高速缓存监视系统总线以尝试写入指令高速缓存中包含的指令的地址。 在这种检测中，指令高速缓存中的该条目无效，并且分支预测高速缓存中的相应条目无效。 随后尝试使用已经无效的分支预测高速缓存中的指令将检测到它无效，并且将转到主存储器以获取已经被修改的指令。