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    Digital computer system with cache controller coordinating both vector and scalar operations
    2.
    发明授权
    Digital computer system with cache controller coordinating both vector and scalar operations 失效
    数字计算机系统与缓存控制器协调矢量和标量运算

    公开(公告)号：US5418973A

    公开(公告)日：1995-05-23

    申请号：US902149

    申请日：1992-06-22

    申请人： James P. Ellis ,  Era Nangia ,  Nital Patwa ,  Bhavin Shah ,  Gilbert M. Wolrich

    发明人： James P. Ellis ,  Era Nangia ,  Nital Patwa ,  Bhavin Shah ,  Gilbert M. Wolrich

    IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F15/80 ,  G06F9/34 ,  G06F13/00

    CPC分类号： G06F15/8092 ,  G06F15/8069 ,  G06F9/30036 ,  G06F9/3834 ,  G06F9/3838

    摘要： A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard. Preferably the cache controller includes vector logic which is responsive to vector information written in intra-processor registers by the execution unit. The vector logic keeps track of the vector length and blocks extra memory addresses generated by the execution unit for the vector elements. The vector logic also blocks the memory addresses of masked vector elements so that these addresses are not translated by the memory management unit.

    摘要翻译： 数字计算机系统包括标量CPU，向量处理器和共享高速缓冲存储器。 标量CPU具有执行单元，存储器管理单元和高速缓存控制器单元。 执行单元生成用于向量加载/存储指令的加载/存储存储器地址。 加载/存储地址由存储器管理单元转换，并存储在也用于缓冲标量写入地址和写入数据的写入缓冲器中。 高速缓存控制器协调 - 在向量处理器和共享缓存之间加载和存储标量读取和写入高速缓存。 优选地，高速缓存控制器通过检查写入队列中的标量写入和向量加载/存储的冲突来允许在标量写入和向量加载/存储之前进行标量读取，并且还允许通过检查与向量的冲突来向量操作之前的向量加载/存储 操作存储在向量注册记分牌中的信息。 优选地，高速缓存控制器包括向量逻辑，其响应于由执行单元写入在处理器内的寄存器中的向量信息。 矢量逻辑跟踪矢量长度，并阻止执行单元为矢量元素生成的额外的存储器地址。 向量逻辑还阻塞被屏蔽向量元素的存储器地址，使得这些地址不被存储器管理单元转换。

    Temporary storage having entries smaller than memory bus
    4.
    发明授权
    Temporary storage having entries smaller than memory bus 失效
    临时存储的条目小于内存总线

    公开(公告)号：US5796976A

    公开(公告)日：1998-08-18

    申请号：US590214

    申请日：1996-01-23

    申请人： Bhavin Shah ,  Era Nangia ,  Gilbert Wolrich ,  Nital Patwa

    发明人： Bhavin Shah ,  Era Nangia ,  Gilbert Wolrich ,  Nital Patwa

    IPC分类号： G06F7/78 ,  G06F13/00 ,  G06F13/14

    CPC分类号： G06F7/78

    摘要： Information is stored in temporary storage and subsequently transferred to a memory over a bus. The temporary storage is provided with a plurality of entries each of which has a selected size that is smaller than a size of the bus. Information that is designated for a common area of the memory is stored in different entries, and the different entries are linked. Before being transferred to memory, the information from linked entries is assembled. The assembled information is then transferred over the bus to memory. Embodiments of the temporary storage include a write queue and a write buffer.

    摘要翻译： 信息存储在临时存储器中，随后通过总线传送到存储器。 临时存储设置有多个条目，每个条目具有小于总线大小的所选大小。 为存储器的公共区域指定的信息存储在不同的条目中，并且不同的条目被链接。 在转移到内存之前，汇编来自链接条目的信息。 然后将汇编的信息通过总线传送到存储器。 临时存储器的实施例包括写入队列和写入缓冲器。

    Circuitry and methodology for pulse capture
    5.
    发明授权
    Circuitry and methodology for pulse capture 失效
    脉冲捕获的电路和方法

    公开(公告)号：US5689454A

    公开(公告)日：1997-11-18

    申请号：US583922

    申请日：1996-01-11

    申请人： Nital Patwa

    发明人： Nital Patwa

    IPC分类号： G11C7/22 ,  G11C15/00

    CPC分类号： G11C7/22

    摘要： Circuitry and methodology for pulse capture employs S-R latch, precharge, and switch circuitries for quickly sensing and capturing a logic pulse from dynamic logic circuitry. The present invention while having general application to any dynamic logic circuitry has particular application to random access memory (RAM), content addressable memory (CAM), and adder circuitries.

    摘要翻译： 用于脉冲捕获的电路和方法采用S-R锁存器，预充电和开关电路，用于快速感测和捕获来自动态逻辑电路的逻辑脉冲。 本发明在一般应用于任何动态逻辑电路时具有对随机存取存储器（RAM），内容寻址存储器（CAM）和加法器电路的特定应用。

    Modified adder tree structure and method using logic and gates to generate carry-in values
    6.
    发明授权
    Modified adder tree structure and method using logic and gates to generate carry-in values 有权
    改进的加法器树结构和方法使用逻辑和门来生成进位值

    公开(公告)号：US6127842A

    公开(公告)日：2000-10-03

    申请号：US344912

    申请日：1999-06-24

    申请人： Parin B. Dalal ,  Steve Hale ,  Stephen C. Purcell ,  Nital Patwa

    发明人： Parin B. Dalal ,  Steve Hale ,  Stephen C. Purcell ,  Nital Patwa

    IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F7/60 ,  H03K19/173

    CPC分类号： G06F7/5318 ,  G06F7/509 ,  G06F7/607

    摘要： In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.

    摘要翻译： 根据本发明，加法器树结构包括至少两个加法器级。 在根据本发明的电路和方法中，两个加法器级中的第一个产生公共权重的两个比特和比公共权重的两个比特重一比特的权重的其他更高有效比特。 两个加法器级中的第二级包括一个加法器，其接收在两个加法器级中的第一级中产生的更高有效位。 第二加法器级还包括与门，其接收和逻辑与公共权重的两个比特以在第二级中产生加法器的进位位。 上述加法器树结构和附加方法具有允许加法器的更多输入端子包含关于加法器树结构的输入值的信息的优点。 因此，加法器被更有效地使用，并且需要较少的加法器来执行特定的功能。

    Decoupling capacitor for integrated circuit signal driver
    7.
    发明授权
    Decoupling capacitor for integrated circuit signal driver 失效
    用于集成电路信号驱动器的去耦电容器

    公开(公告)号：US5883423A

    公开(公告)日：1999-03-16

    申请号：US606138

    申请日：1996-02-23

    申请人： Nital Patwa ,  Jayne Brown-West

    发明人： Nital Patwa ,  Jayne Brown-West

    IPC分类号： H01L27/06 ,  H01L27/092 ,  H01L29/76 ,  H01L29/00

    CPC分类号： H01L27/0688 ,  H01L27/0925

    摘要： A decoupling capacitor for an integrated circuit and method of forming the same. The decoupling capacitor includes a p-channel device having first and second p-type doped diffusion regions, a device channel region therebetween, a device gate overlying the device channel region, and a gate insulator separating the device gate and channel region. The first and second diffusion regions are electrically connected to a positive power supply, and the device gate is electrically connected to a negative power supply. The decoupling capacitor may be formed proximate a signal driver in the integrated circuit. The decoupling capacitor may be formed without additional, expensive semiconductor fabrication steps and operates to minimize noise in the circuit.

    摘要翻译： 用于集成电路的去耦电容器及其形成方法。 去耦电容器包括具有第一和第二p型掺杂扩散区的p沟道器件，其间的器件沟道区，覆盖器件沟道区的器件栅极以及分离器件栅极和沟道区的栅绝缘体。 第一扩散区域和第二扩散区域电连接到正电源，并且器件栅极电连接到负电源。 去耦电容器可以形成在集成电路中的信号驱动器附近。 去耦电容器可以在没有额外的昂贵的半导体制造步骤的情况下形成，并且用于最小化电路中的噪声。

    Program order sequencing of data in a microprocessor with write buffer
    9.
    发明授权
    Program order sequencing of data in a microprocessor with write buffer 失效
    具有写入缓冲器的微处理器中的数据的程序顺序排序

    公开(公告)号：US5740398A

    公开(公告)日：1998-04-14

    申请号：US138651

    申请日：1993-10-18

    申请人： Marc A. Quattromani ,  Nital Patwa

    发明人： Marc A. Quattromani ,  Nital Patwa

    IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08

    CPC分类号： G06F9/30043 ,  G06F12/0855 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3865 ,  G06F12/04

    摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

    摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写入缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。

    Data dependency detection and handling in a microprocessor with write buffer
    10.
    发明授权
    Data dependency detection and handling in a microprocessor with write buffer 失效
    具有写入缓冲器的微处理器中的数据依赖性检测和处理

    公开(公告)号：US5471598A

    公开(公告)日：1995-11-28

    申请号：US139596

    申请日：1993-10-18

    申请人： Marc A. Quattromani ,  Raul A. Garibay, Jr. ,  Nital Patwa ,  Mark W. Hervin

    发明人： Marc A. Quattromani ,  Raul A. Garibay, Jr. ,  Nital Patwa ,  Mark W. Hervin

    IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F13/00

    CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3875

    摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

    摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。