公开(公告)号：US06606676B1

公开(公告)日：2003-08-12

申请号：US09436201

申请日：1999-11-08

申请人： Sanjay Raghunath Deshpande ,  Robert Earl Kruse

发明人： Sanjay Raghunath Deshpande ,  Robert Earl Kruse

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. The node controller also implements an interrupt arbitration scheme designed to choose among multiple eligible interrupt distribution units without using dedicated sideband signals on the bus.

摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。 节点控制器从主设备接收事务，与主设备作为另一个主设备或从设备通信，并对从主设备接收的事务进行排队。 由于一致性的实现在时间和空间上分布，所以节点控制器有助于维持高速缓存一致性。 节点控制器还实现中断仲裁方案，设计用于在多个合格的中断分配单元之间进行选择，而无需在总线上使用专用边带信号。

公开(公告)号：US06516379B1

公开(公告)日：2003-02-04

申请号：US09436204

申请日：1999-11-08

申请人： Sanjay Raghunath Deshpande ,  Robert Earl Kruse

发明人： Sanjay Raghunath Deshpande ,  Robert Earl Kruse

IPC分类号： G06F1300

CPC分类号： G06F12/0813 ,  G06F12/0831

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based ache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to eliminate certain types of snoop collisions by pacing commands selected from its queues in certain circumstances. After a command is selected for snoop from a particular queue, the node controller does not select another command for snoop from that particular queue until the command returns for snoop, at which time the node controller may introduce a configurable delay before allowing a command to be selected from that particular queues.

摘要翻译： 提供了一种使用基于总线的相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。 节点控制器从主设备接收命令，与主设备作为另一个主设备或从设备通信，并对从主设备接收的命令进行排队。 由于一致性的实现在时间和空间上分布，因此节点控制器通过在某些情况下从其队列中选择的起搏命令来帮助消除某些类型的侦听器冲突。 在从特定队列中选择侦听命令之后，节点控制器不会从该特定队列中选择另一个用于侦听的命令，直到该命令返回到侦听，此时节点控制器可以在允许命令为止之前引入可配置的延迟 从该特定队列中选择。

公开(公告)号：US06535941B1

公开(公告)日：2003-03-18

申请号：US09436200

申请日：1999-11-08

申请人： Robert Earl Kruse

发明人： Robert Earl Kruse

IPC分类号： G06F1300

CPC分类号： G06F13/1605 ,  G06F13/362

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. In order to reduce the delays in giving address bus grants, a bus arbiter for a bus connected to a processor and a particular port of the node controller parks the address bus towards the processor. A history of address bus grants is kept to determine whether any of the previous address bus grants could be used to satisfy an address bus request associated with a data bus request. If one of them qualifies, the data bus grant is given immediately, speeding up the data bus grant process by anywhere from one to many cycles depending on the requests for the address bus from the higher priority node controller.

摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。 节点控制器从主设备接收事务，与主设备作为另一个主设备或从设备通信，并对从主设备接收的事务进行排队。 由于一致性的实现在时间和空间上分布，所以节点控制器有助于维持高速缓存一致性。 为了减少给出地址总线授权的延迟，连接到处理器的总线的总线仲裁器和节点控制器的特定端口将地址总线驻留到处理器。 保留地址总线授权的历史以确定是否可以使用先前的地址总线授权中的任何一个来满足与数据总线请求相关联的地址总线请求。 如果其中一个符合条件，则立即给出数据总线授权，根据来自较高优先级节点控制器的地址总线的请求，可以在一到多个周期的任何地方加速数据总线授权过程。

公开(公告)号：US06684279B1

公开(公告)日：2004-01-27

申请号：US09436202

申请日：1999-11-08

申请人： Robert Earl Kruse ,  Robert Allen Drehmel

发明人： Robert Earl Kruse ,  Robert Allen Drehmel

IPC分类号： G06F1200

CPC分类号： G06F13/1657 ,  G06F12/0831 ,  G06F13/364

摘要： A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data bus busy signal is asserted. If the data bus busy signal is asserted, a determination is made regarding whether a data bus grant signal is asserted. If the data bus grant signal is asserted, the next data packet is transferred on the next cycle after a last cycle of data transfer of a previous data packet.

摘要翻译： 描述了用于控制数据传送的方法，装置和计算机程序产品。 检索要传送的下一个数据包。 确定数据总线忙信号是否被断言。 如果数据总线忙信号被置位，则确定是否断言数据总线授权信号。 如果数据总线授权信号被断言，则在先前数据分组的数据传输的最后一个周期之后，下一个周期传送下一个数据分组。

公开(公告)号：US06542949B1

公开(公告)日：2003-04-01

申请号：US09436206

申请日：1999-11-08

申请人： Robert Earl Kruse

发明人： Robert Earl Kruse

IPC分类号： G06F1336

CPC分类号： G06F13/362 ,  G06F13/1605 ,  G06F13/1657

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. In addition, a bus arbiter in the node controller parks a data bus towards a memory subsystem. The node controller does not use data buffer reservations. The data bus grant line to the memory controller is overloaded to use it as a back-pressure, get-off-the-bus signal as well as a normal data bus grant line. The fairness of the bus is thereby increased by creating a mechanism for getting a “parked” device off the data bus without the use of another dedicated signal between physical components. To ensure that the node controller may stream data to the memory subsystem, the bus is not reparked towards the memory subsystem until a configurable number of cycles after the data bus has been granted to the node controller.

摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。 节点控制器从主设备接收事务，与主设备作为另一个主设备或从设备通信，并对从主设备接收的事务进行排队。 由于一致性的实现在时间和空间上分布，所以节点控制器有助于维持高速缓存一致性。 此外，节点控制器中的总线仲裁器将数据总线驻留到存储器子系统。 节点控制器不使用数据缓冲区保留。 到存储器控制器的数据总线授权线路过载，将其用作背压，断开总线信号以及普通数据总线授权线路。 因此，通过创建一种使“停放”设备离开数据总线而不在物理组件之间使用另一个专用信号的机制，从而增加总线的公平性。 为了确保节点控制器可以将数据流传输到存储器子系统，总线不向存储器子系统重放，直到数据总线已被授予节点控制器之后的可配置数量的周期。

公开(公告)号：US06529990B1

公开(公告)日：2003-03-04

申请号：US09436203

申请日：1999-11-08

申请人： Robert Earl Kruse ,  Philip Erna Milling

发明人： Robert Earl Kruse ,  Philip Erna Milling

IPC分类号： G06F1300

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to eliminate certain types of snoop collisions by introducing delays into the snoops of commands selected from its queues in certain circumstances. If the system is lightly loaded, the introduced delay is configured to be the minimum amount necessary to eliminate failed snoops with particular known bus timing conflicts. If the system is more heavily loaded, no delays are experienced in the selection of commands for snoop.

摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。 节点控制器从主设备接收命令，与主设备作为另一个主设备或从设备通信，并对从主设备接收的命令进行排队。 由于一致性的实现在时间和空间上分布，因此节点控制器通过在某些情况下将延迟引入到从其队列中选择的命令的窥探中来帮助消除某些类型的窥探冲突。 如果系统轻载，引入的延迟被配置为消除具有特定已知总线时序冲突的故障侦测所需的最小量。 如果系统负载较重，则在选择窥探命令时不会有延迟。

公开(公告)号：US06523076B1

公开(公告)日：2003-02-18

申请号：US09436192

申请日：1999-11-08

申请人： Robert Earl Kruse

发明人： Robert Earl Kruse

IPC分类号： G06F1300

CPC分类号： G06F13/36

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by node controllers. A node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, a node controller helps to maintain cache coherency. The node controllers must give simultaneous address bus grants to the address switch to initiate a snoop. Livelocks are detected individually by each node controller in an uncoordinated manner from a lack of successful snoops from the address switch to the node controllers. To break the livelock, address bus grants to the address switch are manipulated by the node controllers in a distributed, uncoordinated manner until a snoop is seen by the node controllers, thereby obviating the need for dedicated sideband signals on the bus.

摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统和多个主设备，处理器，I / O代理或相干存储器适配器，被组织成由节点控制器支持的一组节点。 节点控制器从主设备接收事务，与主设备作为另一个主设备或从设备通信，并对从主设备接收的事务进行排队。 由于一致性的实现在时间和空间上分布，节点控制器有助于维持缓存一致性。 节点控制器必须给地址交换机提供同时的地址总线授权以启动窥探。 每个节点控制器以不协调的方式单独检测活动锁，从地址开关到节点控制器的成功窥探不足。 为了断开活动锁，地址总线授予地址开关由节点控制器以分布式，不协调的方式操纵，直到节点控制器看到窥探，从而避免了对总线上专用边带信号的需要。