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1.发明授权Unified memory system architecture including cache and directly addressable static random access memory 有权统一的内存系统架构，包括缓存和直接可寻址的静态随机存取存储器公开(公告)号：US06606686B1
公开(公告)日：2003-08-12
申请号：US09603645
申请日：2000-06-26
申请人： Sanjive Agarwala , Charles L. Fuoco , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
发明人： Sanjive Agarwala , Charles L. Fuoco , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
IPC分类号： G06F1200
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0864 , G06F2212/2515 , G06F2212/601
摘要： A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of ways as directly addressable memory and configuring remaining ways as cache memory. Control logic inhibits indication that tag bits matches address bits and that a cache entry is the least recently used for cache eviction if the corresponding way is configured as directly addressable memory. In an alternative embodiment, the memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of sets equal to 2M, where M is an integer, as cache memory and configuring remaining sets as directly addressable memory.
摘要翻译： 数据处理装置包括中央处理单元和可配置为高速缓冲存储器和可直接寻址存储器的存储器。 存储器可选择性地配置为高速缓冲存储器和可直接寻址的存储器，通过将选定数量的方式配置为直接可寻址存储器并且将剩余方式配置为高速缓冲存储器。 控制逻辑禁止标签位匹配地址位的指示，并且如果相应的方式被配置为直接可寻址存储器，则高速缓存条目是最近最少用于高速缓存驱逐的指示。 在替代实施例中，通过将等于2M的选定数量的集合（其中M是整数）配置为高速缓冲存储器并将剩余集合配置为直接可寻址存储器，可选地将存储器配置为高速缓存存储器和直接寻址存储器。
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2.发明授权Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access 有权多层缓存系统与存储器的一致性有选择地配置为高速缓存或直接访问存储器和直接存储器访问公开(公告)号：US06535958B1
公开(公告)日：2003-03-18
申请号：US09603637
申请日：2000-06-26
申请人： Charles L. Fuoco , Sanjive Agarwala , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
发明人： Charles L. Fuoco , Sanjive Agarwala , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
IPC分类号： G06F1300
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0831 , G06F12/0897
摘要： A data processing system having a central processing unit, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit includes a snoop unit generating snoop accesses to the at least one level one cache upon a direct memory access to the directly addressable memory. The snoop unit generates a write snoop access to both level one caches upon a direct memory access write to or a direct memory access read from the directly addressable memory. The level one cache also invalidates a cache entry upon a snoop hit and also writes back a dirty cache entry to the directly addressable memory. A level two memory is selectively configurable as part level two unified cache and part directly addressable memory.
摘要翻译： 具有中央处理单元，至少一个一级缓存，二级统一高速缓存，直接可寻址存储器和直接存储器访问单元的数据处理系统包括：窥探单元，生成窥探访问至少一级一级高速缓存 直接内存访问直接可寻址的内存。 窥探单元在从直接可寻址存储器读取的直接存储器访问写入或直接存储器访问时，产生对一级缓存的写入窥探访问。 一级缓存还会在侦听命中时使缓存条目无效，并将脏缓存条目写回到可直接寻址的存储器。 二级存储器可选择性地配置为部分二级统一缓存和部分直接可寻址存储器。
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3.发明授权Method and apparatus for operating one or more caches in conjunction with direct memory access controller 有权用于与直接存储器存取控制器一起操作一个或多个高速缓存的方法和装置公开(公告)号：US06594711B1
公开(公告)日：2003-07-15
申请号：US09603057
申请日：2000-06-26
IPC分类号： G06F1300
CPC分类号： G06F12/0802
摘要： A data processing apparatus includes a data processor core having integral cache memory and local memory, and external memory interface and a direct memory access unit. The direct memory access unit is connected to a single data interchange port of the data processor core and to an internal data interchange port of the external memory interface. The direct memory access unit transports data according to commands received from the data processor core to or from devices external to the data processing unit via the external memory interface. As an extension of this invention, a single direct memory access unit may serve a multiprocessing environment including plural data processor cores. The data processor core, external memory interface and direct memory access unit are preferably embodied in a single integrated circuit. The data processor core preferably includes an instruction cache for temporarily storing program instructions and a data cache for temporarily storing data. The data processor core requests direct memory access data transfers for cache service.
摘要翻译： 数据处理装置包括具有集成的高速缓冲存储器和本地存储器以及外部存储器接口和直接存储器存取单元的数据处理器核心。 直接存储器访问单元连接到数据处理器核心的单个数据交换端口和外部存储器接口的内部数据交换端口。 直接存储器访问单元根据从数据处理器核心接收的命令经由外部存储器接口将数据传输到数据处理单元外部的设备或从数据处理单元外部的设备传送。 作为本发明的扩展，单个直接存储器存取单元可以服务于包括多个数据处理器核心的多处理环境。 数据处理器核心，外部存储器接口和直接存储器访问单元优选地体现在单个集成电路中。 数据处理器核心优选地包括用于临时存储程序指令的指令高速缓存和用于临时存储数据的数据高速缓存。 数据处理器核心要求缓存服务的直接内存访问数据传输。
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4.发明授权Unified multilevel memory system architecture which supports both cache and addressable SRAM 有权统一的多层次存储系统架构，支持缓存和可寻址SRAM公开(公告)号：US06484237B1
公开(公告)日：2002-11-19
申请号：US09603365
申请日：2000-06-26
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831 , G06F2212/2515 , G06F2212/601
摘要： A data processing apparatus is embodied in a single integrated circuit. The data processing apparatus includes a central processing unit, at least one level one cache, a level two unified cache and a directly addressable memory. The at least one level one cache preferably includes a level one instruction cache temporarily storing program instructions for execution by the central processing unit and a level one data cache temporarily storing data for manipulation by said central processing unit. The level two unified cache and the directly addressable memory are preferably embodied in a single memory selectively configurable as a part level two unified cache and a part directly addressable memory. The single integrated circuit data processing apparatus further includes a direct memory access unit connected to the directly addressable memory and adapted for connection to an external memory. The direct memory access unit controls data transfer between the directly addressable memory and the external memory.
摘要翻译： 数据处理装置体现在单个集成电路中。 数据处理装置包括中央处理单元，至少一级一级缓存，二级统一缓存和直接寻址存储器。 所述至少一个一级缓存优选地包括一级指令高速缓冲存储器，临时存储由中央处理单元执行的程序指令和一级数据高速缓冲存储器，临时存储用于由所述中央处理单元操纵的数据。 二级统一缓存和直接可寻址存储器优选地体现在可选择性地配置为部分级别二统一高速缓存和部分直接可寻址存储器的单个存储器中。 单个集成电路数据处理装置还包括连接到直接寻址存储器并适于连接到外部存储器的直接存储器存取单元。 直接存储器访问单元控制直接寻址存储器和外部存储器之间的数据传输。
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公开(公告)号：US06665767B1
公开(公告)日：2003-12-16
申请号：US09603333
申请日：2000-06-26
IPC分类号： G06F1200
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0837
摘要： This invention enables a program controlled cache state operation on a program designated address range. The program controlled cache state operation could be writeback of data cached from the program designated address range to a higher level memory or such writeback and invalidation of data cached from the program designated address range. A cache operation unit includes a base address register and a word count register loadable by the central processing unit. The program designated address range is from a base address for a number of words of the word count register. In the preferred embodiment the program controlled cache state operation begins upon loading the word count register. The cache operation unit may operate on fractional cache entries by handling misaligned first and last cycles. Alternatively, The cache operation unit may operate only on whole cache entries. The base address register increments and the word count register decrements until when the word count reaches zero.
摘要翻译： 本发明能够对程序指定的地址范围进行程序控制的高速缓存状态操作。 程序控制的缓存状态操作可以将从程序指定的地址范围缓存的数据写回到较高级别的存储器，或者从程序指定地址范围缓存的数据的这种写回和无效。 高速缓存操作单元包括基地址寄存器和可由中央处理单元加载的字计数寄存器。 程序指定的地址范围是从字计数寄存器的多个字的基地址。 在优选实施例中，程序控制的高速缓存状态操作在加载字计数寄存器时开始。 高速缓存操作单元可以通过处理未对齐的第一和最后一个周期来操作分数缓存条目。 或者，高速缓存操作单元可以仅对整个高速缓存条目进行操作。 基地址寄存器递增，字计数寄存器递减，直到字计数达到零。
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6.发明授权公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译： 描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。 传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。 在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。 使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。
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公开(公告)号：US06954468B1
公开(公告)日：2005-10-11
申请号：US09713423
申请日：2000-11-15
CPC分类号： G06F15/17
摘要： The transfer controller with hub and ports uses a write allocation counter and algorithm to control data reads from a source port. The write allocation count is the amount of data that can be consumed immediately by the write reservation station of a slow destination port and the channel data router buffers. This is used to throttle fast source port read operations to whole read bursts until space to adsorb the read data is available. This ensures that the source port response queue is not blocked with data that cannot be consumed by the channel data router and the slow destination port. This condition would otherwise block a fast source port from providing data to the other destination ports.
摘要翻译： 具有集线器和端口的传输控制器使用写入分配计数器和算法来控制源端口的数据读取。 写分配计数是缓慢目的地端口的写保留站和信道数据路由器缓冲器可以立即消耗的数据量。 这用于将快速源端口读取操作限制为整个读取脉冲串，直到吸收读取数据的空间可用。 这样可确保源端口响应队列不被通道数据路由器和缓慢目标端口不能使用的数据阻塞。 否则，此条件将阻止快速源端口向其他目标端口提供数据。
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公开(公告)号：US06868087B1
公开(公告)日：2005-03-15
申请号：US09713609
申请日：2000-11-15
申请人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco , Christopher L. Mobley
发明人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco , Christopher L. Mobley
CPC分类号： H04L47/6215 , H04L47/50
摘要： A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as a crucial part of the transfer controller. The request queue manager receives these data transfer request packets from plural transfer requests nodes. The request queue manager sorts transfer request packets by their priority level and stores them in the queue manager memory. The request queue manager processes dispatches transfer request packets to a free data channel based upon priority level and first-in-first-out within priority level.
摘要翻译： 具有集线器和端口的传输控制器被视为全局存储器映射的各个位置之间的通信集线器。 请求队列管理器作为传输控制器的关键部分。 请求队列管理器从多个传输请求节点接收这些数据传输请求分组。 请求队列管理器按照优先级排序传输请求数据包，并将其存储在队列管理器内存中。 请求队列管理器根据优先级和优先级别先进先出，处理将传送请求分组分派到空闲数据信道。
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9.发明授权公开(公告)号：US06408345B1
公开(公告)日：2002-06-18
申请号：US09603331
申请日：2000-06-26
IPC分类号： G06F1328
CPC分类号： G06F12/0811 , G06F12/0848 , G06F12/0851 , G06F12/0864 , G06F12/0897 , G06F12/126 , G06F2212/2515 , G06F2212/601
摘要： This invention is a data processing system including a central processing unit executing program instructions to manipulate data, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit adapted for connection to an external memory. A superscalar memory transfer controller schedules plural non-interfering memory movements to and from the level two unified cache and the directly addressable memory each memory cycle in accordance with a predetermined priority of operation. The level one cache preferably includes a level one instruction cache and a level one data cache. The superscalar memory transfer controller is capable of scheduling plural cache tag memory read accesses and one cache tag memory write access in a single memory cycle. The superscalar memory transfer controller is capable of scheduling plural of cache access state machines in a single memory cycle. The superscalar memory transfer controller is capable of scheduling plural memory accesses to non-interfering memory banks of the level two unified cache in a single memory cycle.
摘要翻译： 本发明是一种数据处理系统，包括执行程序指令以操纵数据的中央处理单元，至少一级一级缓存，二级统一缓存，直接寻址存储器和适于连接外部存储器的直接存储器存取单元。 超标量存储器传送控制器根据预定的操作优先级，对来自二级统一高速缓存和直接可寻址存储器的多个非干扰存储器移动进行调度。 一级缓存优选地包括一级指令高速缓存和一级数据高速缓存。 超标量存储器传送控制器能够在单个存储器周期中调度多个缓存标签存储器读取访问和一个缓存标签存储器写访问。 超标量存储器传输控制器能够在单个存储器周期中调度多个高速缓存存取状态机。 超标量存储器传输控制器能够在单个存储器周期中调度对二级统一高速缓存的非干扰存储器组的多个存储器访问。
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公开(公告)号：US06446241B1
公开(公告)日：2002-09-03
申请号：US09615119
申请日：2000-07-13
IPC分类号： G06F1750
CPC分类号： G11C29/56 , G06F12/0831 , G11C29/08
摘要： A method generates a list of allowed states in a cache design by applying each input transaction sequentially to all found legal cache states. If application of an input transaction to a current search cache results in a new cache state, then this new cache state is added to the list of legal cache states and to a list of search cache states. This is repeated for all input transactions and all such found legal cache states. At the same time a sequence of input transactions reaching each new cache state is formed. This new sequence is the sequence of input transactions for the prior cache state and the current input transaction. The method generates a series of test sequences from the list of allowed states and their corresponding sequence of input transactions which are applied to the control logic cache design and to a reference memory. If the response of the control logic cache design fails to match the response of the reference memory, then a design fault is detected.
摘要翻译： 方法通过将每个输入事务顺序地应用于所有找到的合法缓存状态来生成缓存设计中的允许状态列表。 如果将输入事务应用于当前搜索高速缓存导致新的高速缓存状态，则将该新的高速缓存状态添加到合法高速缓存状态列表和搜索高速缓存状态列表。 对于所有输入事务和所有这些发现的合法缓存状态，这是重复的。 同时形成到达每个新的高速缓存状态的一系列输入事务。 此新序列是先前缓存状态和当前输入事务的输入事务序列。 该方法从应用于控制逻辑高速缓存设计和参考存储器的允许状态列表及其相应的输入事务序列生成一系列测试序列。 如果控制逻辑高速缓存设计的响应不符合参考存储器的响应，则检测到设计故障。
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