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公开(公告)号：US5774508A
公开(公告)日：1998-06-30
申请号：US581979
申请日：1996-01-02
CPC分类号： H04L7/0334
摘要： In a data synchronizer a timing error estimator samples a received stream of digitized data symbols at the beginning, end, and a mid-point of a symbol period. These samples are used with a model that assumes that a data stream waveform should transition along a straight line between its values at optimum sampling instances, separated by the symbol period. Differences between a mid-symbol sample estimated using this straight line model and the actual mid-symbol sample are assumed to be due to a timing error. The timing error estimator performs computations on complex inputs and therefore is compatible with a wide variety of modulation types.
摘要翻译： 在数据同步器中，定时误差估计器在符号周期的开始，结束和中点对所接收的数字化数据符号流进行采样。 这些样本与模型一起使用，假定数据流波形应在最佳采样实例之间的直线之间沿直线转换，并以符号周期分隔。 假设使用该直线模型估计的中间符号样本与实际中间符号样本之间的差异被认为是由于定时误差引起的。 定时误差估计器对复杂输入进行计算，因此与各种调制类型兼容。
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2.发明授权Method and apparatus for adaptive filtering in a high interference environment 失效在高干扰环境下进行自适应滤波的方法和装置
公开(公告)号：US5703903A
公开(公告)日：1997-12-30
申请号：US509684
申请日：1995-07-31
CPC分类号： H04L25/03038 , H04L2025/03662
摘要： A method and apparatus for performing adaptive filtering in a high interference environment, such as for a radio, modem, or local area network. The adaptive filtering simultaneously provides interference excision while canceling resultant distortion in the signal caused by synthesizing the notch used to excise the interfering signal. An input signal (13) is pre-filtered (14) and the pre-filtered signal (15) is processed by a rejection filter (12) which combines weighted delayed versions of the pre-filtered signal (40, 42, 44, 46, 48, 50), weighted delayed versions of data decisions corresponding to the same delays as that used in the pre-filtered signal (60, 62, 64, 66, 68, 70), and a post filtered signal (27) to produce the filtered signal (19). The filtered signal (19) is processed by a data and coefficient estimator (18) to provide data decisions (25) and tap weight values (21, 23).
摘要翻译： 一种用于在诸如用于无线电，调制解调器或局域网的高干扰环境中执行自适应滤波的方法和装置。 自适应滤波同时提供干扰切除，同时消除由合成用于消除干扰信号的陷波引起的信号中的结果失真。 输入信号（13）被预滤波（14），并且预滤波信号（15）由拒绝滤波器（12）处理，该滤波器（12）将预滤波信号（40,42,44,46 ，48,50），对应于与预滤波信号（60,62,64,66,68,70）中使用的延迟相同的延迟的数据判定的加权延迟版本，以及后滤波信号（27），以产生 滤波信号（19）。 滤波信号（19）由数据和系数估计器（18）处理以提供数据判定（25）和抽头权重值（21,23）。
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公开(公告)号：US5694440A
公开(公告)日：1997-12-02
申请号：US582840
申请日：1996-01-02
CPC分类号： H03L7/095 , H04L7/0334
摘要： In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.
摘要翻译： 在数据同步器中，定时误差估计器对接收的数据流进行采样并产生时钟以提供数据流的最佳采样，并且锁定检测器监视时钟和接收的数据流以提供是否已经实现最佳采样的指示。 锁定检测器处理基于时钟定时采样的输入的延迟版本之间的差异。 然后，这些采样的差异由非线性电路处理，以提供锁定信号指示，当与预定的阈值信号相比时，其被用于提供最佳采样指示。 锁定检测器对实际和复杂输入进行计算，因此与各种调制类型兼容。 锁定检测器可以在模拟或数字电路中实现，使其适用于广泛的数据同步器应用。
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公开(公告)号：US06724847B1
公开(公告)日：2004-04-20
申请号：US09656006
申请日：2000-09-06
IPC分类号： H04L700
CPC分类号： H04L7/0029 , H04L25/05
摘要： A feed-forward symbol synchronizer (200, FIG. 2) samples symbols transmitted within one or more packets that form a burst of radio frequency (RF) energy. The symbol samples (209) are delayed in a data delay buffer (214) while a phase estimate (212) is generated for each packet. A resampler (218) resamples the delayed symbol samples based on the phase estimate, resulting in resampled data (228) that includes one sample per symbol. The resampled data is clocked into a dual-port RAM (230) using a resampling clock that is also based on the phase estimate. The resampled data is then clocked out of the dual-port RAM and into a demodulator (238) using the receiver's symbol clock (232). Also described are methods of operating the feed-forward symbol synchronizer.
摘要翻译： 前馈符号同步器（200，图2）对形成射频（RF）能量脉冲串的一个或多个分组内传输的符号进行采样。 符号样本（209）在数据延迟缓冲器（214）中延迟，同时为每个分组生成相位估计（212）。 重采样器（218）基于相位估计对延迟的符号采样进行采样，得到每个符号包括一个采样的重采样数据（228）。 重新采样的数据使用也基于相位估计的重采样时钟被计时到双端口RAM（230）。 然后，使用接收机的符号时钟（232）将再采样的数据从双端口RAM中时钟输出到解调器（238）中。 还描述了操作前馈符号同步器的方法。
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5.发明授权Crosspole interference canceling receiver for signals with unrelated baud rates 失效交叉极干扰消除接收机，用于具有无关波特率的信号
公开(公告)号：US5838740A
公开(公告)日：1998-11-17
申请号：US633636
申请日：1996-04-17
摘要： Crosspolarized signals of unrelated baud rates transmitted through a communication channel (10) become depolarized due to channel distortions such as rain and antenna imperfections. The resulting interference is canceled in a Modified Adaptive Crosspole Interference Canceler (MAXPIC) receiver (50, 70) by adjustment the timing in the crosspolarization path to compensate for the differential delay. Near equivalent bit error rate (BER) performance is achieved for systems utilizing crosspolarized signals with independent baud rates. In one embodiment, the receiver uses a fractionally spaced finite impulse response (FIR) filter (78) that operates at an integer multiple of the direct channel signal baud rate. In another embodiment, a variable delay (54) is used to time-align the received crosspolarized channel signal with the crosspolarization interference contained in the received direct signal.
摘要翻译： 通过通信通道（10）传输的无关波特率的交叉偏振信号由于诸如雨和天线缺陷之类的通道失真而被去极化。 通过调整交叉极化路径中的定时以补偿差分延迟，在修改的自适应交叉极间干扰消除器（MAX70）中抵消所产生的干扰。 对于使用具有独立波特率的交叉极化信号的系统，实现了近似等效的误码率（BER）性能。 在一个实施例中，接收机使用在直通信道信号波特率的整数倍下工作的分数间隔的有限脉冲响应（FIR）滤波器（78）。 在另一个实施例中，可变延迟（54）用于将接收的交叉极化信道信号与包含在接收的直接信号中的交叉极化干扰进行时间对准。
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6.发明授权
公开(公告)号：US6085073A
公开(公告)日：2000-07-04
申请号：US33047
申请日：1998-03-02
IPC分类号： H04L27/152 , H04B1/16
CPC分类号： H04L27/1525
摘要： A method and system for reducing the sampling rate of a signal for use with high modulation index frequency modulated signals reduces the power consumption and processing requirements of the digital signal processing equipment which performs the demodulation. In a preferred embodiment, a high modulation index FM signal is divided into in-phase and quadrature phase components by a downconverter (FIG. 1, 10). These components are sampled by analog to digital converters (20, 21) and input to a delay element (40, 41). The resulting delayed and undelayed samples are conveyed to downsamplers (60-63) where the sampling rate is reduced. The undelayed in-phase and delayed quadrature phase components are multiplied together by a first multiplier (70) while the undelayed quadrature phase and delayed in-phase components are multiplied together by a second multiplier (71). The output of the second multiplier (71) is then subtracted from the output of the first multiplier (70) by a subtractor (80) which outputs baseband audio or data.
摘要翻译： 用于降低高调制频率调制信号使用的信号的采样率的方法和系统降低了进行解调的数字信号处理设备的功耗和处理要求。 在优选实施例中，高调制度调频信号通过下变频器被分成同相和正交相分量（图1,10）。 这些组件由模数转换器（20,21）采样并输入到延迟元件（40,41）。 所得到的延迟和未延迟的样品被传送到采样速率降低的下采样器（60-63）。 不延时的同相和延迟正交相位分量由第一乘法器（70）相乘，而不延时正交相位和延迟的同相分量由第二乘法器（71）相乘。 然后，通过输出基带音频或数据的减法器（80）从第一乘法器（70）的输出中减去第二乘法器（71）的输出。
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