公开(公告)号：US20130107633A1

公开(公告)日：2013-05-02

申请号：US13341472

申请日：2011-12-30

申请人： Se Hyun KIM

发明人： Se Hyun KIM

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483

摘要： In a method of reading a nonvolatile memory device, the method comprising, a reading operation of reading data of a selected memory cell; and a read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation succeeds, when it is detected that an error has occurred in the operation of reading data.

摘要翻译： 在一种非易失性存储器件的读取方法中，该方法包括：读取所选存储单元的数据的读取操作; 以及读取重试操作，当检测到在读取数据的操作中发生错误时，通过改变施加到未选择的存储器单元的非选择读取电压直到读取操作成功来执行一个或多个读取操作。

公开(公告)号：US20130099298A1

公开(公告)日：2013-04-25

申请号：US13350519

申请日：2012-01-13

申请人： Se Hyun KIM

发明人： Se Hyun KIM

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/42356 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

摘要： A semiconductor device comprises a buried gate formed in a mat and in an adjacent dummy region. A space larger than is conventional is formed in a dummy region of a mat edge where the buried gate is to be created. This larger space inhibits shortening of an end of a buried gate and reduction in pattern size attributable to lithographic distortion arising between patterned (mat) and unpatterned (dummy) regions. Device reliability is thereby improved by avoiding gap-fill defects of a gate material.

摘要翻译： 半导体器件包括形成在垫中和相邻的虚拟区域中的掩埋栅极。 在要形成掩埋栅的垫边缘的虚拟区域中形成大于常规的空间。 这种更大的空间抑制了掩埋栅极的端部缩短，并且由于在图案化（垫）和未图案化（虚拟）区域之间产生的光刻变形而减小了图案尺寸。 从而通过避免栅极材料的间隙填充缺陷来改善器件的可靠性。

公开(公告)号：US20120134066A1

公开(公告)日：2012-05-31

申请号：US13302375

申请日：2011-11-22

申请人： Hyun Tae KIM ,  Jin Ju PARK ,  Se Hyun KIM ,  Doo Young KIM ,  Kyung Nam HWANG

发明人： Hyun Tae KIM ,  Jin Ju PARK ,  Se Hyun KIM ,  Doo Young KIM ,  Kyung Nam HWANG

IPC分类号： H01G4/008 ,  H01G4/005

CPC分类号： H01G4/008 ,  H01G4/2325 ,  H01G4/30

摘要： There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.

摘要翻译： 提供一种多层陶瓷电容器，其具有通过将双层电极浆料施加到多层陶瓷电容器而形成的双层电极结构。 具有双层电极结构的多层陶瓷电容器包括具有预设长度和宽度的电容器体，并且其中堆叠有多个电介质层，形成在多个电介质层上并具有预设电容的内部电极单元，以及 外部电极单元包括分别形成在电容器主体的两侧以与内部电极电连接的第一外部电极，以及形成在第一外部电极上的第二外部电极。

公开(公告)号：US20120080746A1

公开(公告)日：2012-04-05

申请号：US13315249

申请日：2011-12-08

申请人： Se Hyun KIM

发明人： Se Hyun KIM

IPC分类号： H01L29/78

CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.

摘要翻译： 这里公开了半导体器件的制造方法，以增加半导体器件的操作负担。 一种制造半导体器件的方法包括在半导体衬底中形成凹槽，在凹部的下部形成字线，氧化字线的顶部，以及在凹部的剩余部分中沉积绝缘材料。