公开(公告)号：US20210133025A1

公开(公告)日：2021-05-06

申请号：US16670329

申请日：2019-10-31

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Ara Patapoutian ,  Colin Hill ,  Kurt Walter Getreuer ,  Darshana H. Mehta

IPC: G06F11/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  H03M13/11

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

公开(公告)号：US11086717B2

公开(公告)日：2021-08-10

申请号：US16670329

申请日：2019-10-31

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Ara Patapoutian ,  Colin Hill ,  Kurt Walter Getreuer ,  Darshana H. Mehta

IPC: G06F11/10 ,  G11C16/04 ,  G11C16/26 ,  H03M13/11 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.