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公开(公告)号：US20180349040A1
公开(公告)日：2018-12-06
申请号：US15609651
申请日：2017-05-31
Applicant: Seagate Technology LLC
Inventor： Nitin Satishchandra Kabra , Jackson Ellis , Niranjan Anant Pol , Mark Ish
IPC: G06F3/06 , G06F12/128 , G06F12/0873
Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
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公开(公告)号：US11221956B2
公开(公告)日：2022-01-11
申请号：US15609651
申请日：2017-05-31
Applicant: Seagate Technology LLC
Inventor： Nitin Satishchandra Kabra , Jackson Ellis , Niranjan Anant Pol , Mark Ish
IPC: G06F12/0873 , G06F12/128 , G06F12/02
Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
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公开(公告)号：US12061701B2
公开(公告)日：2024-08-13
申请号：US17165675
申请日：2021-02-02
Applicant: Seagate Technology LLC
Inventor： Hemant Mane , Rajesh Maruti Bhagwat , Avinash Suresh Pisal , Niranjan Anant Pol
CPC classification number: G06F21/572 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F8/65 , G06F9/44589 , G06F13/105 , G06F13/4282 , G06F2213/00
Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.
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公开(公告)号：US12050781B2
公开(公告)日：2024-07-30
申请号：US17991049
申请日：2022-11-21
Applicant: Seagate Technology LLC
Inventor： Jason Wayne Kinsey , Hemant Vitthalrao Mane , Niranjan Anant Pol , Marc Timothy Jones , Jason Matthew Feist
CPC classification number: G06F3/0619 , G06F3/0613 , G06F3/0635 , G06F3/067 , G06F11/1076
Abstract: A data storage system employing distributed memories can have at least one host connected to a plurality of data storage devices via a network controller. One or more performance bottlenecks through the network controller may be identified with a performance module. A peer group consisting of at least two of the plurality of data storage devices is created with the performance module in response to the identified performance bottleneck so that a task can be assigned by the performance module to the peer group. The task may be chosen to mitigate the performance bottleneck by avoiding involvement of the network controller in the task.
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公开(公告)号：US20220075729A1
公开(公告)日：2022-03-10
申请号：US17528977
申请日：2021-11-17
Applicant: Seagate Technology LLC
Inventor： Nitin Satishchandra Kabra , Jackson Ellis , Niranjan Anant Pol , Mark Ish
IPC: G06F12/0873 , G06F12/128 , G06F12/02
Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
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Patent Agency Ranking
公开(公告)号：US20230418685A1
公开(公告)日：2023-12-28
申请号：US18213692
申请日：2023-06-23
Applicant: Seagate Technology LLC
Inventor： Jason Wayne Kinsey , Hemant Vitthalrao Mane , Niranjan Anant Pol , Marc Timothy Jones , Jason Matthew Feist
CPC classification number: G06F9/5083 , G06F3/0613 , G06F3/067 , G06F3/0631 , G06F21/44
Abstract: Method and apparatus for offloading upstream processing tasks to peer groups of downstream data storage devices. A peer control circuit forms a peer group of storage devices in response to a detected processing bottleneck associated with a network controller. One of the storage devices in the peer group is designated as a primary device, and is responsible for interface communications, for subdividing the processing task for execution by secondary devices in the peer group, and coordinating overall execution. The peer group and the processing task are selected to avoid or minimize the processing bottleneck at the network controller level while maintaining ongoing data transfer performance at the storage device level. A list of available device resources and capabilities may be maintained by the peer control circuit. Offloaded tasks can include data rebuilds, cryptographic functions, new device authentication operations, and the like. Multiple overlapping peer groups can be formed as needed.
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公开(公告)号：US20230259661A1
公开(公告)日：2023-08-17
申请号：US17712395
申请日：2022-04-04
Applicant: Seagate Technology LLC
Inventor： Rajesh Maruti Bhagwat , Hemant Vitthalrao Mane , Avinash Suresh Pisal , Niranjan Anant Pol
Abstract: A data storage system can have a hardware interposer connected inline between a plurality of controllers and a plurality of memories. A bus of the hardware interposer may be monitored with a security breach monitor of the hardware interposer to allow a deviation from a predetermined address range to be detected by the security breach monitor, which prompts the security breach monitor to block access through the hardware interposer for a first controller of the plurality of controllers.
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公开(公告)号：US12099642B2
公开(公告)日：2024-09-24
申请号：US17712395
申请日：2022-04-04
Applicant: Seagate Technology LLC
Inventor： Rajesh Maruti Bhagwat , Hemant Vitthalrao Mane , Avinash Suresh Pisal , Niranjan Anant Pol
Abstract: A data storage system can have a hardware interposer connected inline between a plurality of controllers and a plurality of memories. A bus of the hardware interposer may be monitored with a security breach monitor of the hardware interposer to allow a deviation from a predetermined address range to be detected by the security breach monitor, which prompts the security breach monitor to block access through the hardware interposer for a first controller of the plurality of controllers.
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公开(公告)号：US11880568B2
公开(公告)日：2024-01-23
申请号：US17564052
申请日：2021-12-28
Applicant: Seagate Technology LLC
Inventor： Rajesh Maruti Bhagwat , Nahoosh Hemchandra Mandlik , Niranjan Anant Pol , Hemantkumar Vitthalrao Mane
IPC: G06F3/06
CPC classification number: G06F3/0607 , G06F3/0629 , G06F3/0659 , G06F3/0679
Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.
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公开(公告)号：US20230161483A1
公开(公告)日：2023-05-25
申请号：US17991049
申请日：2022-11-21
Applicant: Seagate Technology LLC
Inventor： Jason Wayne Kinsey , Hemant Vitthalrao Mane , Niranjan Anant Pol , Marc Timothy Jones , Jason Matthew Feist
CPC classification number: G06F3/0619 , G06F3/0613 , G06F3/0635 , G06F3/067 , G06F11/1076
Abstract: A data storage system employing distributed memories can have at least one host connected to a plurality of data storage devices via a network controller. One or more performance bottlenecks through the network controller may be identified with a performance module. A peer group consisting of at least two of the plurality of data storage devices is created with the performance module in response to the identified performance bottleneck so that a task can be assigned by the performance module to the peer group. The task may be chosen to mitigate the performance bottleneck by avoiding involvement of the network controller in the task.
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