公开(公告)号：US09954537B1

公开(公告)日：2018-04-24

申请号：US15390453

申请日：2016-12-23

Applicant: Seagate Technology LLC

Inventor： Marcus Marrow ,  Kenneth John Evans ,  Jason Vincent Bellorado

IPC: H03L7/081 ,  H03L7/08 ,  H03L7/18 ,  H03K5/135

CPC classification number: H03L7/08 ,  G06F1/022 ,  H03K5/135 ,  H03L7/0814

Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.

公开(公告)号：US10298240B1

公开(公告)日：2019-05-21

申请号：US15950766

申请日：2018-04-11

Applicant: Seagate Technology LLC

Inventor： Marcus Marrow ,  Kenneth John Evans ,  Jason Vincent Bellorado

IPC: H03L7/081 ,  H03L7/08 ,  H03K5/135 ,  G06F1/04

Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.