公开(公告)号：US20180373302A1

公开(公告)日：2018-12-27

申请号：US15633026

申请日：2017-06-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Pritesh Mahadev Pawaskar

IPC: G06F1/32

Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.

公开(公告)号：US10691190B2

公开(公告)日：2020-06-23

申请号：US15633026

申请日：2017-06-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Pritesh Mahadev Pawaskar

IPC: G06F1/3203 ,  G06F30/367 ,  G06F1/3206 ,  G06F1/26 ,  G06F30/20 ,  G06F119/06

Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.

公开(公告)号：US20190108301A1

公开(公告)日：2019-04-11

申请号：US15725961

申请日：2017-10-05

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Pritesh Mahadev Pawaskar ,  William Harrison Hempy, II ,  Gaurav Mathur

IPC: G06F17/50

Abstract: A method of generating a chip power model (CPM) for a chip by determining a current profile measurement on a validation board for the chip, and stressing the chip using a plurality of stress factors. A stressed measured waveform is captured and stored. A CPM is generated with the measured waveform captured using the plurality of stress factors. A simulation waveform is captured and stored from the CPM. The measured and simulation waveforms are compared, and when the measured and simulation waveforms do not match, at least one parameter of the CPM is modified iteratively until the measured and simulation waveforms match.