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1.发明授权Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications 有权通过增强的节点间通信来加速线路排他性返回到给定处理器的方法和过程公开(公告)号：US08001328B2
公开(公告)日：2011-08-16
申请号：US12021378
申请日：2008-01-29
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016
摘要： A method and apparatus in which the observability of cross-invalidates requests within remote nodes is controlled at the time of a partial response generation, when a remote request initially checks/snoops the directory state of the remote node, but before such the time that the cross-invalidate request is actually sent to the processors on a given node. If all of the remote nodes in the system indicate that the cross-invalidates could be sent during an initial directory snoop, the requesting node is able to return full exclusivity to a given cache line to a requesting processor at the time when it receives all of the partial responses, instead of having to wait for the final responses from each of the remote nodes within the system.
摘要翻译： 当远程请求最初检查/窥探远程节点的目录状态时，而在远程节点的时间之前，在部分响应生成时控制远程节点内的交叉无效请求的可观察性的方法和装置， 交叉无效请求实际上发送给给定节点上的处理器。 如果系统中的所有远程节点指示可以在初始目录窥探期间发送交叉无效信息，则请求节点能够在给定的缓存行接收到所有请求的处理器时向所请求的处理器返回完整的排他性 部分响应，而不必等待系统内每个远程节点的最终响应。
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2.发明授权Apparatus and method for improved data persistence within a multi-node system 有权用于改善多节点系统内的数据持久性的装置和方法公开(公告)号：US08131937B2
公开(公告)日：2012-03-06
申请号：US11766977
申请日：2007-06-22
申请人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0897 , G06F12/126
摘要： Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.
摘要翻译： 改进对对系统有用的保留数据的访问通过管理与多节点系统的处理器相关联的高速缓存的数据流来实现。 可与处理器和存储器阵列一起操作的数据管理设备通过确定沿着哪个数据从处理器中的一个接收到的高速缓存驱逐出的数据返回到主存储器，从而将来自处理器的数据流引导到存储器阵列， 如果可能的话，将被驱逐的数据存储在水平相关的缓存中。
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3.发明申请Method and Process for Expediting the Return of Line Exclusivity to a Given Processor Through Enhanced Inter-node Communications 有权通过增强的节点间通信加速给定处理器的线路独占性返回的方法和过程公开(公告)号：US20090193192A1
公开(公告)日：2009-07-30
申请号：US12021378
申请日：2008-01-29
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016
摘要： Cache coherency latency is reduced through a method and apparatus that expedites the return of line exclusivity to a given processor in a multi-node data handling system through enhanced inter-node communications.
摘要翻译： 通过一种通过增强的节点间通信在多节点数据处理系统中加速线路排他性返回到给定处理器的方法和装置来减少高速缓存一致等待时间。
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4.发明申请Apparatus and Method for Fairness Arbitration for a Shared Pipeline in a Large SMP Computer System 有权大型SMP计算机系统共享管道公平仲裁的装置与方法公开(公告)号：US20090006693A1
公开(公告)日：2009-01-01
申请号：US11768934
申请日：2007-06-27
申请人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
发明人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
IPC分类号： G06F13/14
CPC分类号： G06F13/14 , G06F9/50 , G06F2209/5021 , Y02D10/14 , Y02D10/22
摘要： A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.
摘要翻译： 通过共享流水线访问计算机系统资源的等级优先仲裁的修改，通过允许较高排名的请求仅在较低等级的请求者之前访问共享资源，提供更公平的仲裁。 如果多个请求同时处于活动状态，则排名优先级将首先选择最高优先级的活动请求并授予对资源的访问权限。 它还将设置一个“阻塞锁定”，以防止更高优先级的请求重新获得对资源的访问，直到其余的优先级较低的主动请求者有机会访问该资源。
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5.发明申请Apparatus and Method for Improved Data Persistence within a Multi-node System 有权在多节点系统内改善数据持久性的装置和方法公开(公告)号：US20080320226A1
公开(公告)日：2008-12-25
申请号：US11766977
申请日：2007-06-22
申请人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0897 , G06F12/126
摘要： Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.
摘要翻译： 改进对对系统有用的保留数据的访问通过管理与多节点系统的处理器相关联的缓存的数据流来实现。 可与处理器和存储器阵列一起操作的数据管理设备通过确定沿着哪个数据从处理器中的一个接收到的高速缓存驱逐出的数据返回到主存储器，从而将来自处理器的数据流引导到存储器阵列， 如果可能的话，将被驱逐的数据存储在水平相关的缓存中。
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6.发明申请Method for Expediting Return of Line Exclusivity to a Given Processor in a Symmetric Multiprocessing Data Processing System 失效在对称多处理数据处理系统中加速返回给定处理器的排除独占性的方法公开(公告)号：US20090193194A1
公开(公告)日：2009-07-30
申请号：US12021403
申请日：2008-01-29
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A method and apparatus for eliminating, in a multi-nodes data handling system, contention for exclusivity of lines in cache memory through improved management of system buses, processor cross-invalidate stacks, and the system operations that can lead to these requested cache operations being rejected.
摘要翻译： 一种用于在多节点数据处理系统中消除通过改进的系统总线管理，处理器交叉无效堆栈以及可导致这些所请求的高速缓存操作的系统操作的高速缓冲存储器中线路排他性的争用的方法和装置 拒绝。
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7.发明授权Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效在多节点对称多处理计算机中维护高速缓存一致性公开(公告)号：US08762651B2
公开(公告)日：2014-06-24
申请号：US12821578
申请日：2010-06-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/084
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本 的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。
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8.发明授权Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效在多节点对称多处理计算机中维护高速缓存一致性公开(公告)号：US08423736B2
公开(公告)日：2013-04-16
申请号：US12816464
申请日：2010-06-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。
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9.发明申请Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效维持多节点对称多处理计算机中的缓存一致性公开(公告)号：US20110320738A1
公开(公告)日：2011-12-29
申请号：US12821578
申请日：2010-06-23
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/084
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本 的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。
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10.发明授权Method for ensuring fairness among requests within a multi-node computer system 有权确保多节点计算机系统内的请求之间的公平性的方法公开(公告)号：US07523267B2
公开(公告)日：2009-04-21
申请号：US11532156
申请日：2006-09-15
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.
摘要翻译： 使用包括常规位集合和备用有效位集合的双重有效位集合的方法，其阻止对给定高速缓存行的新请求进入多节点计算机系统的嵌套系统，直到对给定高速缓存行的所有请求已经完成为止 成功了 通过提供替代的有效位，为每个远程请求者提供用于每个远程请求者的两组资源代码，其中一组代码指示资源是否有效并且在该行上主动地工作，而另一组代码指示是否 资源有效，但在请求完成之前遇到一些需要解决的冲突。 只有在成功重新加载和完成远程操作时，这个备用地址有效位复位，并为任何待处理的接口请求继续进行打开方式，因此当前加载到嵌套系统中的本地资源的所有未完成的请求都可以在新界面之前完成 请求被允许进入系统。
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