公开(公告)号：US07006378B1

公开(公告)日：2006-02-28

申请号：US10742987

申请日：2003-12-22

申请人： Tomoya Saito ,  Tomoko Ogura ,  Kimihiro Satoh ,  Seiki Ogura

发明人： Tomoya Saito ,  Tomoko Ogura ,  Kimihiro Satoh ,  Seiki Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.

摘要翻译： 实现非易失性存储器件。 该装置包括一串连接到源极的MONOS电池。 每个MONOS单元包括覆盖衬底中的沟道区的字线门。 第一和第二控制栅极，每个覆盖衬底中的沟道区域。 字线栅极沟道区域横向在第一和第二控制栅极沟道区域之间。 ONO层在控制栅极和衬底之间垂直。 ONO层的氮化物层形成每个控制栅极的电荷存储位置。 在衬底中形成源极和漏极的第一和第二掺杂区域。 字线栅极沟道区和控制栅沟道区在第一掺杂区和第二掺杂区之间。 第一和第二晶体管将最上面的MONOS单元连接到第一位线，将最底部的MONOS单元连接到第二位线。

公开(公告)号：US06670240B2

公开(公告)日：2003-12-30

申请号：US10218210

申请日：2002-08-13

申请人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

发明人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

IPC分类号： H01L21336

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

公开(公告)号：US07118961B2

公开(公告)日：2006-10-10

申请号：US10782358

申请日：2004-02-19

申请人： Tomoko Ogura ,  Tomoya Saito ,  Seiki Ogura ,  Kimihiro Satoh

发明人： Tomoko Ogura ,  Tomoya Saito ,  Seiki Ogura ,  Kimihiro Satoh

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

摘要： In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

公开(公告)号：US20050248984A1

公开(公告)日：2005-11-10

申请号：US11124221

申请日：2005-05-06

申请人： Seiki Ogura ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C5/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/24 ,  H01L27/115

CPC分类号： G11C16/0475 ,  G11C5/025 ,  G11C16/16 ,  G11C16/24 ,  H01L27/115

摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device comprises a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.

摘要翻译： 实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。 该装置包括存储单元阵列区域，其中多个C列和R行存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织包括沿第一方向运行的R行字线，以及 C列的第二方向上延伸的扩散子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个单元通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位 每个单元中的线连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

公开(公告)号：US07190603B2

公开(公告)日：2007-03-13

申请号：US11124221

申请日：2005-05-06

申请人： Seiki Ogura ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C5/06

CPC分类号： G11C16/0475 ,  G11C5/025 ,  G11C16/16 ,  G11C16/24 ,  H01L27/115

摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device includes a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.

摘要翻译： 实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。 该装置包括一个存储单元阵列区域，其中多个C列和R行的存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织由沿第一方向运行的R行字线组成，以及 C列的第二方向上延伸的扩散子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个单元通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位 每个单元中的线连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

公开(公告)号：US06759290B2

公开(公告)日：2004-07-06

申请号：US10107002

申请日：2002-03-26

申请人： Tomoko Ogura ,  Tomoya Saito ,  Seiki Ogura ,  Kimihiro Satoh

发明人： Tomoko Ogura ,  Tomoya Saito ,  Seiki Ogura ,  Kimihiro Satoh

IPC分类号： H01L218238

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

摘要： In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

公开(公告)号：US06998658B2

公开(公告)日：2006-02-14

申请号：US10697925

申请日：2003-10-30

申请人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

发明人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

公开(公告)号：US06825084B2

公开(公告)日：2004-11-30

申请号：US10697520

申请日：2003-10-30

申请人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

发明人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

IPC分类号： H01L21336

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

公开(公告)号：US06477088B2

公开(公告)日：2002-11-05

申请号：US10005932

申请日：2001-12-05

申请人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito

发明人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito

IPC分类号： G11C1604

CPC分类号： G11C16/14 ,  G11C16/0475

摘要： In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.

摘要翻译： 在现有技术中，通过对位扩散施加正偏压和向控制栅极施加负偏压来实现双MONOS存储器擦除。 另一个字栅极和衬底端子接地。 但是由于控制栅极通道长度短，是载波逃逸长度的几倍，因此与控制栅极相邻的字门通道的电压可以显着影响擦除特性和速度。 字门上的负电压提高了擦除速度，而字门下的正通道电位降低了擦除速度。 与现有技术的三阱或物理块分离的擦除阻塞相比，通过存储器阵列的有效偏置，字线或甚至单个存储器单元电平擦除可以没有区域损失。 在没有衬底偏置应用的F-N通道擦除附近，还包括通过字线电压的程序干扰保护。

公开(公告)号：US08174885B2

公开(公告)日：2012-05-08

申请号：US13068066

申请日：2011-05-02

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

IPC分类号： G11C11/34

CPC分类号： G11C16/0475

摘要： The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.teh

摘要翻译： 本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新型读取方法。 在本发明的第一实施例中，替代控制栅极被设置在相同的电压。 在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。 在两个实施例中，位线和字门用于对选定的存储单元进行寻址