公开(公告)号：US20170017543A9

公开(公告)日：2017-01-19

申请号：US14789168

申请日：2015-07-01

Applicant: Seiko Instruments Inc.

Inventor： Masanori MIYAGI ,  Taro YAMASAKI

IPC: G06F11/10 ,  G11C29/36 ,  G11C29/42 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/36 ,  G11C29/42 ,  G11C29/52

Abstract: Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.

Abstract translation: 提供一种非易失性半导体存储装置，其可以用简单的电路进行小型化，而不损害纠错部分的功能，以及测试非易失性半导体存储装置的方法。 错误校正电路被配置为仅执行与数据位相同数量的位的错误检测和校正，并且省略用于执行校验位的错误检测和校正的电路以减小电路的尺寸。 一种多路复用器，用于在测试状态下，用检查位替换从存储元件阵列读出的一部分数据位，并将校验位输入到纠错电路。 因此，执行检查位的错误检测和校正以使得关于校验位的出货检查也是如此。

公开(公告)号：US20150301889A1

公开(公告)日：2015-10-22

申请号：US14789168

申请日：2015-07-01

Applicant: Seiko Instruments Inc.

Inventor： Masanori MIYAGI ,  Taro YAMASAKI

IPC: G06F11/10 ,  G11C29/36 ,  G11C29/42 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/36 ,  G11C29/42 ,  G11C29/52

Abstract: Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.

Abstract translation: 提供一种非易失性半导体存储装置，其可以用简单的电路进行小型化，而不损害纠错部分的功能，以及测试非易失性半导体存储装置的方法。 错误校正电路被配置为仅执行与数据位相同数量的位的错误检测和校正，并且省略用于执行校验位的错误检测和校正的电路以减小电路的尺寸。 一种多路复用器，用于在测试状态下，用检查位替换从存储元件阵列读出的一部分数据位，并将校验位输入到纠错电路。 因此，执行检查位的错误检测和校正以使得关于校验位的出货检查也是如此。