公开(公告)号：US20220254920A1

公开(公告)日：2022-08-11

申请号：US17248750

申请日：2021-02-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Weize Chen ,  Sameer S. Haddad ,  Bruce B. Greenwood ,  Mark Griswold ,  Kenneth A. Bates

IPC: H01L29/788 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

公开(公告)号：US10224323B2

公开(公告)日：2019-03-05

申请号：US15669579

申请日：2017-08-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Moshe Agam ,  Johan Camiel Julia Janssens ,  Jaroslav Pjencak ,  Thierry Yao ,  Mark Griswold ,  Weize Chen

IPC: H01L21/00 ,  H01L27/07 ,  H01L27/088 ,  H01L27/098 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/861 ,  H01L29/78

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

公开(公告)号：US11552193B2

公开(公告)日：2023-01-10

申请号：US17139748

申请日：2020-12-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Weize Chen ,  Mark Griswold ,  Jaroslav Pjencak

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.

公开(公告)号：US11810976B2

公开(公告)日：2023-11-07

申请号：US17178729

申请日：2021-02-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Weize Chen ,  Mark Griswold

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L21/761

CPC classification number: H01L29/7824 ,  H01L21/761 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66681

Abstract: In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

公开(公告)号：US11289613B2

公开(公告)日：2022-03-29

申请号：US16674625

申请日：2019-11-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Weize Chen ,  Mark Griswold

IPC: H01L29/00 ,  H01L29/808 ,  H01L27/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

公开(公告)号：US20210119059A1

公开(公告)日：2021-04-22

申请号：US16674625

申请日：2019-11-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Weize Chen ,  Mark Griswold

IPC: H01L29/808 ,  H01L27/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

公开(公告)号：US11545583B2

公开(公告)日：2023-01-03

申请号：US17248750

申请日：2021-02-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Weize Chen ,  Sameer S. Haddad ,  Bruce B. Greenwood ,  Mark Griswold ,  Kenneth A. Bates

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.