公开(公告)号：US20180366588A1

公开(公告)日：2018-12-20

申请号：US16053188

申请日：2018-08-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Satoshi SHINOHARA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

公开(公告)号：US20170069765A1

公开(公告)日：2017-03-09

申请号：US15356976

申请日：2016-11-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Satoshi SHINOHARA

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78693

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract translation: 提供一种晶体管，其具有为此目的所必需的电特性，并且使用氧化物半导体层和包括晶体管的半导体器件。 在其中至少栅极电极层，栅极绝缘膜和半导体层依次层叠的底栅晶体管中，包含能量间隙彼此不同的至少两个氧化物半导体层的氧化物半导体层叠层 用作半导体层。 可以将氧和/或掺杂剂添加到氧化物半导体堆叠层。

公开(公告)号：US20160071983A1

公开(公告)日：2016-03-10

申请号：US14933392

申请日：2015-11-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Satoshi SHINOHARA

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78693

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

公开(公告)号：US20210313473A1

公开(公告)日：2021-10-07

申请号：US17308658

申请日：2021-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Satoshi SHINOHARA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

公开(公告)号：US20140217401A1

公开(公告)日：2014-08-07

申请号：US14244401

申请日：2014-04-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masahiko HAYAKAWA ,  Satoshi SHINOHARA

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78606

Abstract: Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less. The taper angle θ of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.

Abstract translation: 提供了一种包括氧化物半导体的底栅晶体管，其中当高电平时，可能在漏电极层的端部附近（和源电极层的端部附近）可能发生的电场浓度 对栅电极层施加栅极电压而抑制了开关特性的劣化，提高了可靠性。 与通道形成区域重叠的绝缘层的截面形状为锥形。 与通道形成区域重叠的绝缘层的厚度为0.3μm以下，优选为5nm以上0.1μm以下。 锥角＆thetas; 与沟道形成区域重叠的绝缘层的横截面形状的下端部分为60°以下，优选为45°以下，进一步优选为30°以下。

公开(公告)号：US20230275159A1

公开(公告)日：2023-08-31

申请号：US18107559

申请日：2023-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Satoshi SHINOHARA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/78696 ,  H01L29/7869 ,  H01L29/786 ,  H01L29/78693 ,  H01L29/045 ,  H01L29/24

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

公开(公告)号：US20200243689A1

公开(公告)日：2020-07-30

申请号：US16847912

申请日：2020-04-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Satoshi SHINOHARA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

公开(公告)号：US20150115263A1

公开(公告)日：2015-04-30

申请号：US14590133

申请日：2015-01-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Satoshi SHINOHARA

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78693

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract translation: 提供一种晶体管，其具有为此目的所必需的电特性，并且使用氧化物半导体层和包括晶体管的半导体器件。 在其中至少栅极电极层，栅极绝缘膜和半导体层依次层叠的底栅晶体管中，包含能量间隙彼此不同的至少两个氧化物半导体层的氧化物半导体层叠层 用作半导体层。 可以将氧和/或掺杂剂添加到氧化物半导体堆叠层。

公开(公告)号：US20140256096A1

公开(公告)日：2014-09-11

申请号：US14284857

申请日：2014-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Satoshi SHINOHARA ,  Miki SUZUKI ,  Hideto OHNUMA

IPC: H01L29/66

CPC classification number: H01L29/66772 ,  H01L27/1288 ,  H01L29/66492 ,  H01L29/78624

Abstract: A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.

Abstract translation: 提供了一种半导体器件，其包括形成在绝缘表面上并具有源极区，漏极区和沟道形成区的单晶半导体层，覆盖单晶半导体层的栅极绝缘膜和与 沟道形成区域之间插入栅极绝缘膜。 在半导体器件中，源极和漏极区域的至少漏极区域包括与沟道形成区域相邻的第一杂质区域和与第一杂质区域相邻的第二杂质区域。 与深度方向上的第二杂质区域的杂质浓度分布的最大值相比，深度方向上的第一杂质区域的杂质浓度分布的最大值比绝缘面更接近。

公开(公告)号：US20130082253A1

公开(公告)日：2013-04-04

申请号：US13626226

申请日：2012-09-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masahiko HAYAKAWA ,  Satoshi SHINOHARA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78606

Abstract: Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less. The taper angle 0 of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.

Abstract translation: 提供了一种包括氧化物半导体的底栅晶体管，其中当高电平时，可能在漏电极层的端部附近（和源电极层的端部附近）可能发生的电场浓度 对栅电极层施加栅极电压而抑制了开关特性的劣化，提高了可靠性。 与通道形成区域重叠的绝缘层的截面形状为锥形。 与通道形成区域重叠的绝缘层的厚度为0.3μm以下，优选为5nm以上0.1μm以下。 与通道形成区域重叠的绝缘层的截面形状的下端部的锥角θ为60°以下，优选为45°以下，进一步优选为30°以下。