公开(公告)号：US20100065919A1

公开(公告)日：2010-03-18

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L27/092

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07902609B2

公开(公告)日：2011-03-08

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L23/62

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07642148B2

公开(公告)日：2010-01-05

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US20080079087A1

公开(公告)日：2008-04-03

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07785951B2

公开(公告)日：2010-08-31

申请号：US11831223

申请日：2007-07-31

申请人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US20080081476A1

公开(公告)日：2008-04-03

申请号：US11831223

申请日：2007-07-31

申请人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/302 ,  H01L21/31

CPC分类号： H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US20080272436A1

公开(公告)日：2008-11-06

申请号：US11853187

申请日：2007-09-11

申请人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/283

CPC分类号： H01L21/823807 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.

摘要翻译： 半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜 第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。 半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔 层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔 暴露第三栅电极的界面区域。 形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔 形成了。

公开(公告)号：US07759185B2

公开(公告)日：2010-07-20

申请号：US11853187

申请日：2007-09-11

申请人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.

摘要翻译： 半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜 第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。 半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔 层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔 暴露第三栅电极的界面区域。 形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔 形成了。

公开(公告)号：US20070178644A1

公开(公告)日：2007-08-02

申请号：US11698070

申请日：2007-01-26

申请人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

发明人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

IPC分类号： H01L21/336

CPC分类号： H01L21/3212 ,  H01L21/76801 ,  H01L21/7684

摘要： A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

摘要翻译： 提供了当执行金属化学机械抛光（CMP）时具有降低（或最小）腐蚀性能的电介质或绝缘层的半导体器件及其制造方法。 半导体器件可以包括形成在衬底上的栅电极。 第一层间氧化物层可以形成在衬底上和栅电极之间。 可以在第一层间氧化物层上形成比第一层间氧化物层硬的第二层间氧化物层。 可以通过第二层间氧化物层和第一层间氧化物层形成插塞电极。

公开(公告)号：US20080081406A1

公开(公告)日：2008-04-03

申请号：US11750491

申请日：2007-05-18

申请人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

发明人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

IPC分类号： H01L29/739

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

摘要翻译： 一种制造半导体器件的方法，包括在PMOS区上提供包括PMOS区和PMOS栅电极的NMOS区和在NMOS栅区上的NMOS栅电极的衬底，所述衬底在形成的PMOS区上形成应力衬垫 PMOS晶体管上的PMOS栅极和NMOS区域上形成有NMOS栅电极的NMOS区域，并以惰性蒸气气氛，选择性地将辐射施加到形成在PMOS区域和NMOS区域中的任一个上的应力衬垫上。