公开(公告)号：US08621296B2

公开(公告)日：2013-12-31

申请号：US13165304

申请日：2011-06-21

申请人： Seok-Il Kwon ,  Hoijin Lee

发明人： Seok-Il Kwon ,  Hoijin Lee

IPC分类号： G01R31/28

CPC分类号： G01R31/318577 ,  G01R31/318541

摘要： An integrated circuit device includes first and second latches (e.g, D-type flip flops) responsive to a clock signal. Each of the first and second latches respectively includes a data input terminal, a scan input terminal, a scan enable terminal and an output terminal. A combinational logic circuit may be provided, which is configured to receive the signal from the output terminal of the first latch and configured to generate a signal at the data input terminal of the second latch. A scan path is also provided, which is responsive to a scan enable signal. The scan path is configured to selectively pass a signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is active. A power saving switch is also provided. This switch, which is responsive to the scan enable signal, includes a first current carrying terminal electrically coupled to the scan path. The switch is configured to disable the scan path from passing the signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is in an inactive state.

摘要翻译： 集成电路装置包括响应于时钟信号的第一和第二锁存器（例如，D型触发器）。 第一和第二锁存器中的每一个分别包括数据输入端子，扫描输入端子，扫描使能端子和输出端子。 可以提供组合逻辑电路，其被配置为从第一锁存器的输出端子接收信号，并被配置为在第二锁存器的数据输入端产生信号。 还提供扫描路径，其响应于扫描使能信号。 扫描路径被配置为当扫描使能信号有效时，将信号从第一锁存器的输出端子选择性地传递到第二锁存器的扫描输入端子。 还提供省电开关。 响应于扫描使能信号的该开关包括电耦合到扫描路径的第一载流端子。 当扫描使能信号处于非活动状态时，开关被配置为禁止扫描路径将信号从第一锁存器的输出端子传递到第二锁存器的扫描输入端子。

公开(公告)号：US20120215959A1

公开(公告)日：2012-08-23

申请号：US13342440

申请日：2012-01-03

申请人： Seok-Il Kwon ,  Hoijin Lee

发明人： Seok-Il Kwon ,  Hoijin Lee

IPC分类号： G06F12/08

CPC分类号： G06F12/0846 ,  G06F12/0855

摘要： Disclosed is a cache memory controlling method for reducing cache latency. The method includes sending a target address to a tag memory storing tag data and sending the target address to a second group data memory that has a latency larger than that of a first group data memory. The method further includes generating and outputting a cache signal that indicates whether the first group data memory includes target data and that indicates whether the second group data memory includes target data. The target address is sent to the second group data memory before the output of the cache signal. With an exemplary embodiment, cache latency is minimized or reduced, and the performance of a cache memory system is improved.

摘要翻译： 公开了一种用于减少高速缓存延迟的缓存存储器控制方法。 该方法包括将目标地址发送到存储标签数据的标签存储器，并将目标地址发送到具有比第一组数据存储器的等待时间更长的等待时间的第二组数据存储器。 该方法还包括产生和输出指示第一组数据存储器是否包括目标数据并且指示第二组数据存储器是否包括目标数据的高速缓存信号。 在缓存信号输出之前，将目标地址发送到第二组数据存储器。 利用示例性实施例，高速缓存等待时间被最小化或减少，并且提高了高速缓冲存储器系统的性能。

公开(公告)号：US20110320896A1

公开(公告)日：2011-12-29

申请号：US13165304

申请日：2011-06-21

申请人： Seok-Il Kwon ,  Hoijin Lee

发明人： Seok-Il Kwon ,  Hoijin Lee

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318577 ,  G01R31/318541

摘要： An integrated circuit device includes first and second latches (e.g, D-type flip flops) responsive to a clock signal. Each of the first and second latches respectively includes a data input terminal, a scan input terminal, a scan enable terminal and an output terminal. A combinational logic circuit may be provided, which is configured to receive the signal from the output terminal of the first latch and configured to generate a signal at the data input terminal of the second latch. A scan path is also provided, which is responsive to a scan enable signal. The scan path is configured to selectively pass a signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is active. A power saving switch is also provided. This switch, which is responsive to the scan enable signal, includes a first current carrying terminal electrically coupled to the scan path. The switch is configured to disable the scan path from passing the signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is in an inactive state.

摘要翻译： 集成电路装置包括响应于时钟信号的第一和第二锁存器（例如，D型触发器）。 第一和第二锁存器中的每一个分别包括数据输入端子，扫描输入端子，扫描使能端子和输出端子。 可以提供组合逻辑电路，其被配置为从第一锁存器的输出端子接收信号，并被配置为在第二锁存器的数据输入端产生信号。 还提供扫描路径，其响应于扫描使能信号。 扫描路径被配置为当扫描使能信号有效时，将信号从第一锁存器的输出端子选择性地传递到第二锁存器的扫描输入端子。 还提供省电开关。 响应于扫描使能信号的该开关包括电耦合到扫描路径的第一载流端子。 当扫描使能信号处于非活动状态时，开关被配置为禁止扫描路径将信号从第一锁存器的输出端子传递到第二锁存器的扫描输入端子。

公开(公告)号：US08981494B2

公开(公告)日：2015-03-17

申请号：US13615034

申请日：2012-09-13

申请人： Seok Il Kwon ,  Hoijin Lee ,  Hyejoo Lee

发明人： Seok Il Kwon ,  Hoijin Lee ,  Hyejoo Lee

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

CPC分类号： G06F17/505 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807

摘要： The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks or scan paths without completely re-working an integrated circuit. The process may be referred to as an engineering change order (ECO) process. According to an exemplary process a buffer may be reconfigured to operate as a NAND gate, a NOR gate, or an INVERTER, for example, and may be configured to operate in a circuit in need of such a logic function.

摘要翻译： 逻辑单元的功能可以通过改变它们的金属布线来改变。 以这种方式改变的逻辑单元可用于校正，替代或以其他方式改变逻辑块或扫描路径的操作，而不必完全重新集成电路。 该过程可以被称为工程变更单（ECO）过程。 根据示例性处理，可以将缓冲器重新配置为例如与NAND门，NOR门或INVERTER一起工作，并且可以被配置为在需要这种逻辑功能的电路中工作。

公开(公告)号：US20130069169A1

公开(公告)日：2013-03-21

申请号：US13615034

申请日：2012-09-13

申请人： Seok-Il Kwon ,  Hoijin Lee ,  Hyejoo Lee

发明人： Seok-Il Kwon ,  Hoijin Lee ,  Hyejoo Lee

IPC分类号： H01L27/085 ,  H01L21/768 ,  G06F17/50

CPC分类号： G06F17/505 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807

摘要： The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks or scan paths without completely re-working an integrated circuit. The process may be referred to as an engineering change order (ECO) process. According to an exemplary process a buffer may be reconfigured to operate as a NAND gate, a NOR gate, or an INVERTER, for example, and may be configured to operate in a circuit in need of such a logic function.

摘要翻译： 逻辑单元的功能可以通过改变它们的金属布线来改变。 以这种方式改变的逻辑单元可用于校正，替代或以其他方式改变逻辑块或扫描路径的操作，而不必完全重新集成电路。 该过程可以被称为工程变更单（ECO）过程。 根据示例性处理，可以将缓冲器重新配置为例如与NAND门，NOR门或INVERTER一起工作，并且可以被配置为在需要这种逻辑功能的电路中工作。

公开(公告)号：US09214925B2

公开(公告)日：2015-12-15

申请号：US13440007

申请日：2012-04-05

申请人： Hoijin Lee ,  Bai-Sun Kong

发明人： Hoijin Lee ,  Bai-Sun Kong

IPC分类号： H03L5/00 ,  H03K3/356

CPC分类号： H03K3/356121

摘要： A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

摘要翻译： 时钟选通电路包括脉冲发生器和脉冲电平移位器。 脉冲发生器由第一电源电压驱动，并被配置为接收时钟信号以产生脉冲和反相脉冲。 脉冲电平移位器由比第一电源电压高的第二电源电压驱动，并被配置为接收脉冲和反相脉冲，并响应于使能信号转换脉冲电平。

公开(公告)号：US08451040B2

公开(公告)日：2013-05-28

申请号：US12963174

申请日：2010-12-08

申请人： Hoijin Lee ,  Gunok Jung

发明人： Hoijin Lee ,  Gunok Jung

IPC分类号： H03K3/356

CPC分类号： H03K3/037 ,  H03K3/012 ,  H03K3/356104

摘要： A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.

摘要翻译： 触发电路包括：输入部，其通过第一外部输入端子接收第一外部输入信号;存储部，其存储从输入部发送的信号;以及输出部，其输出存储在存储部中的信号，通过 外部输出端子作为对通过输入部分的第二外部输入端子接收的第二外部输入信号的逻辑运算结果。 输出部分包括直接连接到外部输出端的逻辑门，逻辑门的输入端接收存储在存储部分中的信号。