公开(公告)号：US09214925B2

公开(公告)日：2015-12-15

申请号：US13440007

申请日：2012-04-05

申请人： Hoijin Lee ,  Bai-Sun Kong

发明人： Hoijin Lee ,  Bai-Sun Kong

IPC分类号： H03L5/00 ,  H03K3/356

CPC分类号： H03K3/356121

摘要： A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

摘要翻译： 时钟选通电路包括脉冲发生器和脉冲电平移位器。 脉冲发生器由第一电源电压驱动，并被配置为接收时钟信号以产生脉冲和反相脉冲。 脉冲电平移位器由比第一电源电压高的第二电源电压驱动，并被配置为接收脉冲和反相脉冲，并响应于使能信号转换脉冲电平。

公开(公告)号：US20130241594A1

公开(公告)日：2013-09-19

申请号：US13890517

申请日：2013-05-09

申请人： Hoi-Jin LEE ,  Bai-Sun KONG

发明人： Hoi-Jin LEE ,  Bai-Sun KONG

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K3/356182

摘要： A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.

摘要翻译： 扫描触发器电路包括输入单元和输出单元。 数据输出单元被配置为在第一操作模式中响应于数据输入信号和第一控制信号向数据输出端提供数据输出信号，并且数据输出单元被配置为禁止数据输出端 在第二操作模式中响应于数据输入信号和第一控制信号，提供施加到扫描触发器电路的电源电压和接地电压。 扫描输出单元被配置为在第二操作模式中响应于扫描输入信号和第二控制信号向扫描输出端提供扫描输出信号。

公开(公告)号：US07928792B2

公开(公告)日：2011-04-19

申请号：US12367398

申请日：2009-02-06

申请人： Bai-Sun Kong ,  Byung-Hwa Jung ,  Sung-Chan Kang

发明人： Bai-Sun Kong ,  Byung-Hwa Jung ,  Sung-Chan Kang

IPC分类号： H03L5/00

CPC分类号： H03K19/01735

摘要： Disclosed herein is an apparatus for outputting complementary signals using bootstrapping technology. The apparatus for outputting complementary signals includes a precharaged logic block, one or more output nodes, and a bootstrapping circuit block. The precharged differential logic block generates a differential signal depending on an input signal. The one or more output nodes output the complementary signals depending on the differential signal. The bootstrapping circuit block is shared by the one or more output nodes, and amplifies the complementary signals.

摘要翻译： 本文公开了一种使用自举技术输出互补信号的装置。 用于输出互补信号的装置包括预先存储的逻辑块，一个或多个输出节点和自举电路块。 预充电差分逻辑块根据输入信号产生差分信号。 一个或多个输出节点根据差分信号输出互补信号。 自举电路块由一个或多个输出节点共享，并放大互补信号。

公开(公告)号：US20100207684A1

公开(公告)日：2010-08-19

申请号：US12691937

申请日：2010-01-22

申请人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

发明人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

摘要翻译： 提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。 在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

公开(公告)号：US20090134937A1

公开(公告)日：2009-05-28

申请号：US12287620

申请日：2008-10-10

申请人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

发明人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

IPC分类号： G05F1/10

CPC分类号： G11C5/145

摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.

摘要翻译： 电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。 升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。 第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。 第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。 第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

公开(公告)号：US20080023761A1

公开(公告)日：2008-01-31

申请号：US11819606

申请日：2007-06-28

申请人： Mu-Kyeng Jung ,  Xiao Quan Wang ,  Bai-Sun Kong

发明人： Mu-Kyeng Jung ,  Xiao Quan Wang ,  Bai-Sun Kong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66659

摘要： Semiconductor devices and methods of fabricating the same are provided. According to an example embodiment, a semiconductor device may include an active region disposed in a substrate and having first conductivity type impurity ions, a gate electrode crossing on the active region, a source region disposed within the active region at one a first side of the gate electrode, a drain region disposed within the active region at the a second side of the gate electrode, a source lightly doped drain (LDD) region disposed within the active region, extending toward the gate electrode from the source region, and having second conductivity type impurity ions, a drain LDD region disposed within the active region, extending toward the gate electrode from the drain region, and having the second conductivity type impurity ions in a concentration higher than the source LDD region, and a first halo region disposed within the active region, surrounding the source LDD region, and having the first conductivity type impurity ions.

摘要翻译： 提供半导体器件及其制造方法。 根据示例性实施例，半导体器件可以包括设置在衬底中并具有第一导电类型杂质离子的有源区，在有源区上交叉的栅电极，设置在有源区的第一侧的源极区 栅电极，设置在所述栅电极的第二侧的有源区内的漏极区，设置在所述有源区内的源极轻掺杂漏极（LDD）区，从所述源极区朝向所述栅电极延伸，并具有第二导电性 设置在有源区内的漏极LDD区域，从漏区延伸到栅电极，并且具有浓度高于源极LDD区域的第二导电型杂质离子，以及设置在该源极LDD区域内的第一晕圈区域 有源区，围绕源LDD区，并具有第一导电类型的杂质离子。

公开(公告)号：US06211704B1

公开(公告)日：2001-04-03

申请号：US09371836

申请日：1999-08-11

申请人： Bai-Sun Kong

发明人： Bai-Sun Kong

IPC分类号： A03K19096

CPC分类号： G06F7/505 ,  G06F7/501 ,  G06F7/503 ,  G06F7/507 ,  G06F2207/3872 ,  G06F2207/3884 ,  G11C11/412 ,  H03K3/356147 ,  H03K19/0019 ,  H03K19/0963 ,  H03K19/1738 ,  H03K19/215

摘要： An asynchronous sensing differential logic circuit using a charge-recycling technique includes a control block carrying out a logical operation on a request signal from a preceding stage and a request signal for a succeeding stage, and outputting a first or second input enable signal and a first or second clock signal, a functional block carrying out an operation on an input data according to the first or second input enable signals and the first or second clock signals from the control block, and outputting a first or second output enable signal and an output data, and a latch block triggered by an acknowledge signal from the succeeding stage, and outputting a request signal for the succeeding stage and a final output data by carrying out an operation on the first or second output enable signals and the output data from the functional block.

摘要翻译： 使用电荷再循环技术的异步感测差分逻辑电路包括对来自前级的请求信号执行逻辑运算的控制块和后级的请求信号，以及输出第一或第二输入使能信号和第一 或第二时钟信号，根据第一或第二输入使能信号和来自控制块的第一或第二时钟信号对输入数据执行操作的功能块，并输出第一或第二输出使能信号和输出数据 以及由来自后级的确认信号触发的锁存块，并且通过对来自功能块的第一或第二输出使能信号和输出数据执行操作来输出后级的请求信号和最终输出数据 。

公开(公告)号：US08441279B2

公开(公告)日：2013-05-14

申请号：US13154731

申请日：2011-06-07

申请人： Hoi-Jin Lee ,  Bai-Sun Kong

发明人： Hoi-Jin Lee ,  Bai-Sun Kong

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K3/356182

摘要： A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage level at the selected output terminal bidirectionally transitions between a first voltage level and a second voltage level. A voltage level at a non-selected output terminal unidirectionally transitions between the first voltage level and the second voltage level.

摘要翻译： 扫描触发器电路包括输入单元和输出单元。 输入单元根据操作模式选择数据输入信号和扫描输入信号之一，并基于所选择的信号产生中间信号。 输出单元基于中间信号产生输出信号，并根据操作模式选择数据输出端和扫描输出端之一，以通过所选择的输出端提供输出信号。 所选择的输出端子处的电压电平在第一电压电平和第二电压电平之间双向转换。 未选择的输出端子处的电压电平在第一电压电平和第二电压电平之间单向转变。

公开(公告)号：US20120268182A1

公开(公告)日：2012-10-25

申请号：US13440007

申请日：2012-04-05

申请人： HOIJIN LEE ,  Bai-Sun Kong

发明人： HOIJIN LEE ,  Bai-Sun Kong

IPC分类号： H03K3/00 ,  H03H11/26

CPC分类号： H03K3/356121

摘要： A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

摘要翻译： 时钟选通电路包括脉冲发生器和脉冲电平移位器。 脉冲发生器由第一电源电压驱动，并被配置为接收时钟信号以产生脉冲和反相脉冲。 脉冲电平移位器由比第一电源电压高的第二电源电压驱动，并被配置为接收脉冲和反相脉冲，并响应于使能信号转换脉冲电平。

公开(公告)号：US08130028B2

公开(公告)日：2012-03-06

申请号：US12691937

申请日：2010-01-22

申请人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

发明人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

IPC分类号： G05F3/02

CPC分类号： H02M3/07

摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

摘要翻译： 提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。 在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。