公开(公告)号：US20060242524A1

公开(公告)日：2006-10-26

申请号：US10906388

申请日：2005-02-17

申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

公开(公告)号：US20070005290A1

公开(公告)日：2007-01-04

申请号：US11160601

申请日：2005-06-30

申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

IPC分类号： G01K1/00

CPC分类号： G01K3/14 ,  G01K3/10

摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.

摘要翻译： 用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。 确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。 温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。 该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。

公开(公告)号：US20060095905A1

公开(公告)日：2006-05-04

申请号：US10904259

申请日：2004-11-01

申请人： Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

发明人： Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

IPC分类号： G06F9/46

CPC分类号： G06F9/485

摘要： A method for servicing threads within a multi-processor system is disclosed. In response to an input/output (I/O) request to a peripheral by a thread, a latency time is assigned to the thread such that the thread will not be interrogated until the latency time has lapsed. After the latency time is lapsed, a determination is made as to whether or not the I/O request has been responded. If the I/O request has not been responded after the latency time is lapsed, the latency time is assigned to the thread again. Otherwise, if the I/O request has been responded after the latency time is lapsed, the latency time is updated with an actual response time. The actual response time is from a time when the I/O request was made to a time when the I/O request was actually responded.

摘要翻译： 公开了一种用于在多处理器系统内维护线程的方法。 响应于线程对外设的输入/输出（I / O）请求，延迟时间被分配给线程，使得在延迟时间过去之前线程将不被询问。 在延迟时间过去之后，确定I / O请求是否已被响应。 如果延迟时间过后I / O请求未被响应，则延迟时间将再次分配给该线程。 否则，如果在延迟时间过后已经响应了I / O请求，则延迟时间将以实际响应时间更新。 实际的响应时间是从I / O请求到实际响应I / O请求时的时间。

公开(公告)号：US20070006108A1

公开(公告)日：2007-01-04

申请号：US11160609

申请日：2005-06-30

申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Stanley Stanski

发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Stanley Stanski

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a communication structure included within the library.

摘要翻译： 集成电路（IC）架构包括被配置为提供多个单独电路功能的知识产权（IP）核心库。 所述IP核以与所述IP核中的各个IP核的定制功能选择相兼容的方式布置，其中通过包括在所述库内的通信结构来访问单独选择的核。

公开(公告)号：US20070101332A1

公开(公告)日：2007-05-03

申请号：US11163746

申请日：2005-10-28

申请人： Adam Courchesne ,  Francis Kampf ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski

发明人： Adam Courchesne ,  Francis Kampf ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski

IPC分类号： G06F9/46

CPC分类号： G06F9/5011 ,  G06F2209/507 ,  G06F2209/508

摘要： Thread entries are stored in a memory of the system to indicate executed instruction threads. Uses of processing resources by the respective instruction threads are detected and history entries for the threads are stored in a memory of the system. Such history entries indicate whether respective processing resources have been used by respective ones of the instruction threads. The history entries of first and second ones of the instruction threads are compared. The second instruction thread is selected for executing if the comparing indicates history of processing resources used by the first thread has a certain difference relative to history of processing resources used by the second thread.

摘要翻译： 线程条目存储在系统的存储器中以指示执行的指令线程。 检测各个指令线程使用的处理资源，并将线程的历史条目存储在系统的存储器中。 这些历史条目表示相应的指令线程是否已经使用相应的处理资源。 比较第一和第二条指令线程的历史条目。 如果比较指示由第一线程使用的处理资源的历史与第二线程使用的处理资源的历史有一定差异，则选择第二指令线程来执行。

公开(公告)号：US20070266349A1

公开(公告)日：2007-11-15

申请号：US11382371

申请日：2006-05-09

申请人： Jesse Craig ,  Scott Vento ,  Stanley Stanski ,  Andrew Wienick

发明人： Jesse Craig ,  Scott Vento ,  Stanley Stanski ,  Andrew Wienick

IPC分类号： G06F17/50 ,  G06F11/00 ,  G01R31/28

CPC分类号： G01R31/318385 ,  G06F11/263

摘要： A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested coverage event, and finds a logical, deterministic crossover point between at least two test cases. Once a pair of test cases with at least one crossover point has been identified the method crosses a portion of the random number trace up to the crossover point with a portion of the second random number trace, which continues from the crossover point. The result is a new random number trace that is a combination of a portion of one test and a portion of another test. The new random number trace is sent to the stimulus generator as the new random number input.

摘要翻译： 定向随机验证系统和方法从生成的测试用例池中分析一对生成的测试用例，该测试用例能够测试至少一部分未经测试的覆盖事件，并在至少两个测试之间找到逻辑的确定性交叉点 案件 一旦已经确定了具有至少一个交叉点的一对测试用例，该方法将随机数曲线的一部分与第二随机数迹线的一部分交叉到交叉点，该部分从交叉点继续。 结果是一个新的随机数迹线，它是一个测试的一部分和另一个测试的一部分的组合。 新的随机数字轨迹作为新的随机数输入发送到刺激发生器。

公开(公告)号：US20050256984A1

公开(公告)日：2005-11-17

申请号：US10844530

申请日：2004-05-13

申请人： Peter Jenkins ,  Paul Mattos ,  Stanley Stanski

发明人： Peter Jenkins ,  Paul Mattos ,  Stanley Stanski

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4072

摘要： The invention is directed to determining the link integrity using information in a industry standard connection protocol, such as the Peripheral Component Interconnect Express® industry standard system level bus interconnect protocol. One or more features required in the industry standard protocol are used to implement a loopback master and a loopback slave in an interface device (also referred to as an interface) and an external component or device. Using such features may consume less logic area and provide a robust environment for checking link integrity and capabilities.

摘要翻译： 本发明涉及使用工业标准连接协议中的信息来确定链路完整性，诸如外围组件互连高速（R）工业标准系统级总线互连协议。 行业标准协议中所需的一个或多个功能用于在接口设备（也称为接口）和外部组件或设备中实现环回主站和回送从站。 使用这些功能可能会消耗更少的逻辑区域，并提供一个强大的环境来检查链路的完整性和能力。