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11 条记录 (耗时 0.021 秒)

    METHOD AND APPARATUS FOR RESOURCE-BASED THREAD ALLOCATION IN A MULTIPROCESSOR COMPUTER SYSTEM
    1.
    发明申请
    METHOD AND APPARATUS FOR RESOURCE-BASED THREAD ALLOCATION IN A MULTIPROCESSOR COMPUTER SYSTEM 审中-公开
    在多处理器计算机系统中基于资源的线程分配的方法和装置

    公开(公告)号：US20070101332A1

    公开(公告)日：2007-05-03

    申请号：US11163746

    申请日：2005-10-28

    申请人： Adam Courchesne ,  Francis Kampf ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski

    发明人： Adam Courchesne ,  Francis Kampf ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski

    IPC分类号： G06F9/46

    CPC分类号： G06F9/5011 ,  G06F2209/507 ,  G06F2209/508

    摘要： Thread entries are stored in a memory of the system to indicate executed instruction threads. Uses of processing resources by the respective instruction threads are detected and history entries for the threads are stored in a memory of the system. Such history entries indicate whether respective processing resources have been used by respective ones of the instruction threads. The history entries of first and second ones of the instruction threads are compared. The second instruction thread is selected for executing if the comparing indicates history of processing resources used by the first thread has a certain difference relative to history of processing resources used by the second thread.

    摘要翻译： 线程条目存储在系统的存储器中以指示执行的指令线程。 检测各个指令线程使用的处理资源，并将线程的历史条目存储在系统的存储器中。 这些历史条目表示相应的指令线程是否已经使用相应的处理资源。 比较第一和第二条指令线程的历史条目。 如果比较指示由第一线程使用的处理资源的历史与第二线程使用的处理资源的历史有一定差异，则选择第二指令线程来执行。

    SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION
    2.
    发明申请
    SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION 失效
    系统与片上互连验证的系统和方法

    公开(公告)号：US20060242524A1

    公开(公告)日：2006-10-26

    申请号：US10906388

    申请日：2005-02-17

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR SYSTEM
    3.
    发明申请
    METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR SYSTEM 审中-公开
    用于在多处理器系统中维护螺纹的方法和装置

    公开(公告)号：US20060095905A1

    公开(公告)日：2006-05-04

    申请号：US10904259

    申请日：2004-11-01

    申请人： Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

    发明人： Adam Courchesne ,  Kenneth Goodnow ,  Gregory Mann ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

    IPC分类号： G06F9/46

    CPC分类号： G06F9/485

    摘要： A method for servicing threads within a multi-processor system is disclosed. In response to an input/output (I/O) request to a peripheral by a thread, a latency time is assigned to the thread such that the thread will not be interrogated until the latency time has lapsed. After the latency time is lapsed, a determination is made as to whether or not the I/O request has been responded. If the I/O request has not been responded after the latency time is lapsed, the latency time is assigned to the thread again. Otherwise, if the I/O request has been responded after the latency time is lapsed, the latency time is updated with an actual response time. The actual response time is from a time when the I/O request was made to a time when the I/O request was actually responded.

    摘要翻译： 公开了一种用于在多处理器系统内维护线程的方法。 响应于线程对外设的输入/输出（I / O）请求，延迟时间被分配给线程，使得在延迟时间过去之前线程将不被询问。 在延迟时间过去之后，确定I / O请求是否已被响应。 如果延迟时间过后I / O请求未被响应，则延迟时间将再次分配给该线程。 否则，如果在延迟时间过后已经响应了I / O请求，则延迟时间将以实际响应时间更新。 实际的响应时间是从I / O请求到实际响应I / O请求时的时间。

    METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE THROUGH DETERMINISTIC PATH DELAYS
    5.
    发明申请
    METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE THROUGH DETERMINISTIC PATH DELAYS 失效
    通过确定性延迟监测集成电路温度的方法和装置

    公开(公告)号：US20070005290A1

    公开(公告)日：2007-01-04

    申请号：US11160601

    申请日：2005-06-30

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth Goodnow ,  Jason Norman ,  Stanley Stanski ,  Scott Vento

    IPC分类号： G01K1/00

    CPC分类号： G01K3/14 ,  G01K3/10

    摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.

    摘要翻译： 用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。 确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。 温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。 该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。

    Data acknowledgment using impedance mismatching
    8.
    发明申请
    Data acknowledgment using impedance mismatching 失效
    使用阻抗失配的数据确认

    公开(公告)号：US20050076170A1

    公开(公告)日：2005-04-07

    申请号：US10680756

    申请日：2003-10-07

    申请人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

    发明人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4269

    摘要： A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.

    摘要翻译： 一种用于控制半导体器件上的数据流的结构和相关方法。 在半导体器件内形成发射器，接收器和传输线。 发射器，接收器和传输线适于控制半导体器件内的第一芯和第二芯之间的数据传输。 发射机适于通过传输线路将信号发送到适于接收信号的接收机。 接收机还适于产生阻抗失配以指示第二核心不能传送数据。 发射机适用于检测阻抗失配。

    System and method for system-on-chip interconnect verification
    9.
    发明申请
    System and method for system-on-chip interconnect verification 有权
    系统级芯片互连验证的系统和方法

    公开(公告)号：US20080215945A1

    公开(公告)日：2008-09-04

    申请号：US11819748

    申请日：2007-06-28

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/3177 ,  G06F13/00 ,  G06F11/25

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    System and method for system-on-chip interconnect verification
    10.
    发明授权
    System and method for system-on-chip interconnect verification 有权
    系统级芯片互连验证的系统和方法

    公开(公告)号：US07865789B2

    公开(公告)日：2011-01-04

    申请号：US11819748

    申请日：2007-06-28

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。