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13 条记录 (耗时 0.03 秒)

    Method and apparatus for monitoring integrated circuit temperature through deterministic path delays
    1.
    发明授权
    Method and apparatus for monitoring integrated circuit temperature through deterministic path delays 失效
    通过确定性路径延迟监测集成电路温度的方法和装置

    公开(公告)号：US07275011B2

    公开(公告)日：2007-09-25

    申请号：US11160601

    申请日：2005-06-30

    申请人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01K7/01

    CPC分类号： G01K3/14 ,  G01K3/10

    摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.

    摘要翻译： 用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。 确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。 温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。 该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。

    System and method for system-on-chip interconnect verification
    2.
    发明授权
    System and method for system-on-chip interconnect verification 失效
    系统级芯片互连验证的系统和方法

    公开(公告)号：US07313738B2

    公开(公告)日：2007-12-25

    申请号：US10906388

    申请日：2005-02-17

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    System and method for system-on-chip interconnect verification
    3.
    发明申请
    System and method for system-on-chip interconnect verification 有权
    系统级芯片互连验证的系统和方法

    公开(公告)号：US20080215945A1

    公开(公告)日：2008-09-04

    申请号：US11819748

    申请日：2007-06-28

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/3177 ,  G06F13/00 ,  G06F11/25

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    System and method for system-on-chip interconnect verification
    4.
    发明授权
    System and method for system-on-chip interconnect verification 有权
    系统级芯片互连验证的系统和方法

    公开(公告)号：US07865789B2

    公开(公告)日：2011-01-04

    申请号：US11819748

    申请日：2007-06-28

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    Chip lockout protection scheme for integrated circuit devices and insertion thereof
    8.
    发明授权
    Chip lockout protection scheme for integrated circuit devices and insertion thereof 失效
    集成电路器件的芯片锁定保护方案及其插入

    公开(公告)号：US08484481B2

    公开(公告)日：2013-07-09

    申请号：US12764144

    申请日：2010-04-21

    申请人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G06F21/00

    CPC分类号： G06F21/31 ,  G06F2221/2127

    摘要： A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

    摘要翻译： 一种用于实现用于IC设备的芯片锁定保护方案的系统包括存储由用户外部输入的密码的片上密码寄存器; 片上安全块，根据外部输入的密码是否匹配正确的密码，产生芯片解锁信号; 片上虚拟数据发生器; 输入保护方案，被配置为在输入正确的密码时将外部数据输入门控到功能芯片电路; 以及通信中的输出保护方案，被配置为在输入正确的密码时将真实芯片数据引导到IC设备的外部输出，并且在输入不正确的密码时将由伪数据生成器产生的假数据转换到外部输出。 由假数据发生器产生的错误是确定性的，并且基于外部数据输入，从而混淆是否输入了正确的密码。

    Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof
    9.
    发明申请
    Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof 失效
    集成电路器件芯片锁定保护方案及其插入

    公开(公告)号：US20110016326A1

    公开(公告)日：2011-01-20

    申请号：US12764144

    申请日：2010-04-21

    申请人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G06F21/00

    CPC分类号： G06F21/31 ,  G06F2221/2127

    摘要： A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

    摘要翻译： 一种用于实现用于IC设备的芯片锁定保护方案的系统包括存储由用户外部输入的密码的片上密码寄存器; 片上安全块，根据外部输入的密码是否匹配正确的密码，产生芯片解锁信号; 片上虚拟数据发生器; 输入保护方案，被配置为在输入正确的密码时将外部数据输入门控到功能芯片电路; 以及通信中的输出保护方案，被配置为在输入正确的密码时将真实芯片数据引导到IC设备的外部输出，并且在输入不正确的密码时将由伪数据生成器产生的假数据转换到外部输出。 由假数据发生器产生的错误是确定性的，并且基于外部数据输入，从而混淆是否输入了正确的密码。