公开(公告)号：US07882403B2

公开(公告)日：2011-02-01

申请号：US11633424

申请日：2006-12-05

申请人： Seung-Chul Hong ,  Jong-Han Lim

发明人： Seung-Chul Hong ,  Jong-Han Lim

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/2703

摘要： Provided is an apparatus and method for controlling an interleaver/deinterleaver memory in a mobile communication system are provided. In particular, an apparatus and method are provided which can reduce unnecessary time and power consumption by eliminating an unnecessary memory erasure. A write address generator generates write addresses. A memory stores values mapped to the write addresses. A memory controller controls the memory in which an input signal is accumulated to a value stored at a write address which is then recorded at the write address if the value stored at the write address is recorded for a previous packet when the input signal is generated. The memory controller controls the memory in which the input signal is recorded at the write address if the value stored at the current record address is a valid value for a current packet.

摘要翻译： 提供了一种用于控制移动通信系统中的交织器/去交织器存储器的装置和方法。 特别地，提供了一种通过消除不必要的存储器擦除来减少不必要的时间和功耗的装置和方法。 写地址生成器生成写入地址。 存储器存储映射到写地址的值。 存储器控制器将输入信号被累加的存储器控​​制在存储在写地址处的值，然后当产生输入信号时，如果存储在写地址处的值被记录在先前的分组中，则写入地址被记录。 如果当前记录地址中存储的值是当前数据包的有效值，则存储器控制器控制输入信号在写入地址处被记录的存储器。

公开(公告)号：US20070047623A1

公开(公告)日：2007-03-01

申请号：US11511505

申请日：2006-08-29

申请人： Yoo-Chang Eun ,  Seung-Chul Hong ,  Jong-Han Lim

发明人： Yoo-Chang Eun ,  Seung-Chul Hong ,  Jong-Han Lim

IPC分类号： H04B1/00

CPC分类号： H04J13/10 ,  G06F7/584 ,  H04B1/70756

摘要： A method and apparatus are provided for generating a code by quickly computing a state of a Linear Feedback Shift Register (LFSR) in a mobile communication system, in which a code for the communication system is generated including an n-stage LFSR and operating in sleep mode and active mode set at a preset time interval from the sleep mode. Current state values of the LFSR are combined with n different mask patterns such that the current state values are shifted by {20,21, . . . ,2n−1}. A combination result is provided as a new state value of the LFSR at an arbitrary time variably set in the sleep mode. To transform a current state value of the LFSR to a new state value after an arbitrary time, the code generation method employs a square and multiply algorithm without use of mask patterns.

摘要翻译： 提供了一种用于通过在移动通信系统中快速计算线性反馈移位寄存器（LFSR）的状态来生成代码的方法和装置，其中生成包括n级LFSR并在睡眠中操作的通信系统的代码 模式和活动模式设置为从睡眠模式预设的时间间隔。 LFSR的当前状态值与n个不同的掩模图案组合，使得当前状态值偏移{2 <0> 0，2 <1> 1。 。 。 ，2-n-1}。 组合结果作为在睡眠模式下可变地设置的任意时间的LFSR的新状态值被提供。 为了在任意时间之后将LFSR的当前状态值变换为新的状态值，代码生成方法采用平方和乘法算法而不使用掩码模式。

公开(公告)号：US20070150775A1

公开(公告)日：2007-06-28

申请号：US11633424

申请日：2006-12-05

申请人： Seung-Chul Hong ,  Jong-Han Lim

发明人： Seung-Chul Hong ,  Jong-Han Lim

IPC分类号： G06F11/00

CPC分类号： H03M13/2703

摘要： Provided is an apparatus and method for controlling an interleaver/deinterleaver memory in a mobile communication system are provided. In particular, an apparatus and method are provided which can reduce unnecessary time and power consumption by eliminating an unnecessary memory erasure. A write address generator generates write addresses. A memory stores values mapped to the write addresses. A memory controller controls the memory in which an input signal is accumulated to a value stored at a write address which is then recorded at the write address if the value stored at the write address is recorded for a previous packet when the input signal is generated. The memory controller controls the memory in which the input signal is recorded at the write address if the value stored at the current record address is a valid value for a current packet.

摘要翻译： 提供了一种用于控制移动通信系统中的交织器/去交织器存储器的装置和方法。 特别地，提供了一种通过消除不必要的存储器擦除来减少不必要的时间和功耗的装置和方法。 写地址生成器生成写入地址。 存储器存储映射到写地址的值。 存储器控制器将输入信号被累加的存储器控​​制在存储在写地址处的值，然后当产生输入信号时，如果存储在写地址处的值被记录在先前的分组中，则写入地址被记录。 如果当前记录地址中存储的值是当前数据包的有效值，则存储器控制器控制输入信号在写入地址处被记录的存储器。

公开(公告)号：US08548075B2

公开(公告)日：2013-10-01

申请号：US12947667

申请日：2010-11-16

申请人： Seung-Chul Hong ,  Anand Anandakumar ,  Curtis Ling

发明人： Seung-Chul Hong ,  Anand Anandakumar ,  Curtis Ling

IPC分类号： H04K1/10

CPC分类号： H04L1/0023 ,  H04L5/0007 ,  H04L7/0016 ,  H04L25/0216 ,  H04L27/265 ,  H04L27/2665 ,  H04L27/2671 ,  H04L27/2695

摘要： Systems and methods for adjusting timing in a communication system, such as an OFDM system are described. In one implementation an error signal is generated to adjust the timing of a variable rate interpolator so as to adjust FFT timing. The error signal may be based on detection of significant peaks in an estimate of the impulse response of the channel, with the peak locations being tracked over subsequent symbols and the system timing adjusted in response to changes in the peaks.

公开(公告)号：US07136410B2

公开(公告)日：2006-11-14

申请号：US10331946

申请日：2002-12-31

申请人： In-Kyeong Choi ,  Young-Ho Jung ,  Seong-Rag Kim ,  Seung-Chul Hong ,  Yong-Hoon Lee

发明人： In-Kyeong Choi ,  Young-Ho Jung ,  Seong-Rag Kim ,  Seung-Chul Hong ,  Yong-Hoon Lee

IPC分类号： H04B1/707 ,  H03H7/40

CPC分类号： H04B1/71055 ,  H04B1/7115 ,  H04B7/04 ,  H04B7/0854 ,  H04L2025/03605

摘要： An adaptive interference suppression receiver for a DS/CDMA system includes: input signal generators outputting a part of received signals of receiver antennas that has a coding block's transfer code; adaptive filter blocks filtering a complex signal output from the input signal generators with a tap weight updated based on a constraint MMSE criterion and estimating phase and amplitude components of a specific user channel using the filtering output signal to generate a channel-estimated signal; a signal restorer combining the channel-estimated signal and the filtering output signal and restoring an original signal; a signal selector for selecting known training data signal or the restored signal; and error generators comparing the channel-estimated signal and the filtering output signal and calculating an error between the two signals.

摘要翻译： 用于DS / CDMA系统的自适应干扰抑制接收机包括：输入信号发生器，其输出具有编码块传输码的接收机天线的一部分接收信号; 自适应滤波器块利用基于约束MMSE标准更新的抽头权重来过滤来自输入信号发生器的复合信号，并且使用滤波输出信号估计特定用户信道的相位和幅度分量以产生信道估计信号; 组合信道估计信号和滤波输出信号并恢复原始信号的信号恢复器; 用于选择已知训练数据信号或恢复信号的信号选择器; 和误差发生器比较信道估计信号和滤波输出信号，并计算两个信号之间的误差。

公开(公告)号：US20110287725A1

公开(公告)日：2011-11-24

申请号：US12947779

申请日：2010-11-16

申请人： Seung-Chul Hong ,  Sheng Ye ,  Tienyu Chang

发明人： Seung-Chul Hong ,  Sheng Ye ,  Tienyu Chang

IPC分类号： H04W52/52 ,  H04W88/02

CPC分类号： H04B7/0814

摘要： A transmitting/receiving circuit includes, in part, at least one transceiver, and at least two receiving channels forming a diversity receiver. One of the receiving channels includes, in part, a saw filter, an amplifier, and a frequency converter. The other receiving channel includes, in part, an amplifier, a frequency converter, and a received signal strength indicator (RSSI) adapted to detect signals transmitted by the transceiver. The RSSI is optionally coupled to an input terminal of its associated amplifier. The receiver further includes, in part, at least one processor operative to combine signals processed through the first and second receiving channels using a weight the processor assigns to the signal received by the second receiving channel in accordance with a strength of the blocker signal that the RSSI detects. The second receiving channel optionally includes an RSSI.

摘要翻译： 发送/接收电路部分地包括至少一个收发器和至少两个形成分集接收器的接收信道。 其中一个接收通道部分包括锯式滤波器，放大器和变频器。 另一个接收信道部分地包括适于检测由收发机发送的信号的放大器，频率转换器和接收信号强度指示符（RSSI）。 RSSI可选地耦合到其相关放大器的输入端。 所述接收机还部分包括至少一个处理器，其操作以通过所述处理器根据所述阻塞信号的强度根据所述第二接收信道接收到的信号来组合通过所述第一和第二接收信道处理的信号， RSSI检测。 第二接收信道可选地包括RSSI。

公开(公告)号：US09392547B2

公开(公告)日：2016-07-12

申请号：US13014539

申请日：2011-01-26

申请人： Seung-Chul Hong ,  Sheng Ye ,  Tienyu Chang ,  Anand K. Anandkumar

发明人： Seung-Chul Hong ,  Sheng Ye ,  Tienyu Chang ,  Anand K. Anandkumar

IPC分类号： H04L1/02 ,  H04W52/02 ,  H04B7/08

CPC分类号： H04W52/0264 ,  H04B7/0871 ,  Y02D70/122 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/444

摘要： A diversity receiver includes a first receiving channel and a second receiving channel. The receiver also includes a baseband processor that computes a difference between the received signal strengths of the signals received from the first and second channels, wherein the processor disables the signal received from the second channel if the difference is greater than a first threshold value and a BER associated with the second receiving channel is greater than a BER threshold value, and disables the signal received from the first channel if the difference is less than the negative first threshold value and the bit error rate (BER) associated with the first channel is greater than the BER threshold value. The receiver further includes a bypass circuit coupled to an input of an amplifier and a RSSI circuit that provides a conduction path between the input and a ground when the RSSI circuit detects a blocker signal.

摘要翻译： 分集接收机包括第一接收信道和第二接收信道。 接收机还包括基带处理器，其计算从第一和第二信道接收的信号的接收信号强度之间的差异，其中如果差值大于第一阈值，则处理器禁用从第二信道接收的信号， 与第二接收信道相关联的BER大于BER阈值，并且如果差小于负第一阈值并且与第一信道相关联的误码率（BER）较大，则禁用从第一信道接收的信号 比BER阈值。 接收器还包括耦合到放大器的输入端的旁路电路和当RSSI电路检测到阻塞信号时在输入和地之间提供导通路径的RSSI电路。

公开(公告)号：US09014103B2

公开(公告)日：2015-04-21

申请号：US11842833

申请日：2007-08-21

申请人： Hi-Chan Moon ,  Seung-Chul Hong

发明人： Hi-Chan Moon ,  Seung-Chul Hong

IPC分类号： H04W4/00 ,  H04W74/00 ,  H04W74/08

CPC分类号： H04W74/004 ,  H04W74/0833 ,  H04W74/0866

摘要： A method for transmitting a preamble over a Random Access CHannel (RACH) in a wireless communication system is provided. The method includes generating a preamble having a length longer than a basic transmission unit, and dividing the preamble into preambles having a length less than the basic transmission unit; and sequentially transmitting the divided preambles over the RACH using different antennas.

摘要翻译： 提供了一种用于在无线通信系统中通过随机接入信道（RACH）发送前同步码的方法。 该方法包括生成比基本传输单元长的长度的前同步码，并将该前导码分割为长度小于基本传输单元的前导码; 并且使用不同的天线在RACH上顺序发送分割​​的前同步码。

公开(公告)号：US20110280349A1

公开(公告)日：2011-11-17

申请号：US12947667

申请日：2010-11-16

申请人： Seung-Chul Hong ,  Anand Anandakumar ,  Curtis Ling

发明人： Seung-Chul Hong ,  Anand Anandakumar ,  Curtis Ling

IPC分类号： H04L7/00 ,  H04L27/06

CPC分类号： H04L1/0023 ,  H04L5/0007 ,  H04L7/0016 ,  H04L25/0216 ,  H04L27/265 ,  H04L27/2665 ,  H04L27/2671 ,  H04L27/2695

摘要： Systems and methods for adjusting timing in a communication system, such as an OFDM system are described. In one implementation an error signal is generated to adjust the timing of a variable rate interpolator so as to adjust FFT timing. The error signal may be based on detection of significant peaks in an estimate of the impulse response of the channel, with the peak locations being tracked over subsequent symbols and the system timing adjusted in response to changes in the peaks.

摘要翻译： 描述了用于调整诸如OFDM系统的通信系统中的定时的系统和方法。 在一个实现中，产生误差信号以调整可变速率内插器的定时，以便调整FFT定时。 误差信号可以基于在通道的脉冲响应的估计中检测到有效峰值，其中峰值位置在随后的符号上被跟踪，并且响应于峰值的变化来调整系统时序。

公开(公告)号：US09231685B2

公开(公告)日：2016-01-05

申请号：US12947779

申请日：2010-11-16

申请人： Seung-Chul Hong ,  Sheng Ye ,  Tienyu Chang

发明人： Seung-Chul Hong ,  Sheng Ye ,  Tienyu Chang

IPC分类号： H04B17/00 ,  H04B7/08

CPC分类号： H04B7/0814

摘要： A transmitting/receiving circuit includes, in part, at least one transceiver, and at least two receiving channels forming a diversity receiver. One of the receiving channels includes, in part, a saw filter, an amplifier, and a frequency converter. The other receiving channel includes, in part, an amplifier, a frequency converter, and a received signal strength indicator (RSSI) adapted to detect signals transmitted by the transceiver. The RSSI is optionally coupled to an input terminal of its associated amplifier. The receiver further includes, in part, at least one processor operative to combine signals processed through the first and second receiving channels using a weight the processor assigns to the signal received by the second receiving channel in accordance with a strength of the blocker signal that the RSSI detects. The second receiving channel optionally includes an RSSI.

摘要翻译： 发送/接收电路部分地包括至少一个收发器和至少两个形成分集接收器的接收信道。 其中一个接收通道部分包括锯式滤波器，放大器和变频器。 另一个接收信道部分地包括适于检测由收发机发送的信号的放大器，频率转换器和接收信号强度指示符（RSSI）。 RSSI可选地耦合到其相关放大器的输入端。 所述接收机还部分包括至少一个处理器，其操作以通过所述处理器根据所述阻塞信号的强度根据所述第二接收信道接收到的信号来组合通过所述第一和第二接收信道处理的信号， RSSI检测。 第二接收信道可选地包括RSSI。