公开(公告)号：US20120154006A1

公开(公告)日：2012-06-21

申请号：US13048185

申请日：2011-03-15

申请人： Seung-Joon AHN ,  Jong-Chern Lee

发明人： Seung-Joon AHN ,  Jong-Chern Lee

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.

摘要翻译： 占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比 信号并输出​​检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

公开(公告)号：US20120154002A1

公开(公告)日：2012-06-21

申请号：US13400967

申请日：2012-02-21

申请人： Seung-Joon AHN ,  Jong-Chern Lee

发明人： Seung-Joon AHN ,  Jong-Chern Lee

IPC分类号： H03L7/08

CPC分类号： H03L7/0816 ,  H03L7/0814

摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

摘要翻译： 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。

公开(公告)号：US20110156766A1

公开(公告)日：2011-06-30

申请号：US12753442

申请日：2010-04-02

申请人： Seung-Joon AHN ,  Jong-Chern Lee

发明人： Seung-Joon AHN ,  Jong-Chern Lee

IPC分类号： H03L7/00 ,  H03L7/06

CPC分类号： H03L7/0816 ,  H03L7/0814

摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

摘要翻译： 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。