-
公开(公告)号:US20220413579A1
公开(公告)日:2022-12-29
申请号:US17398218
申请日:2021-08-10
摘要: A wireless device includes a voltage regulator circuit configured to generate a voltage signal of a first input voltage, and a wireless baseband processing circuitry (WBPC) coupled to the voltage regulator circuit to receive the voltage signal. The WBPC is configured to process signals for transmission or reception using wireless technology. The WBPC includes a sub-system processor circuit configured to detect a wireless bandwidth of an application executing on an application processor of the wireless device; determine a second input voltage based on the wireless bandwidth of the application and a maximum voltage supported by the WBPC; and encode a feedback signal for communication to the voltage regulator circuit. The feedback signal causes adjustment of the voltage signal to the second input voltage.
-
公开(公告)号:US20230324981A1
公开(公告)日:2023-10-12
申请号:US17702270
申请日:2022-03-23
申请人: Arvind Sundaram , Santhosh Ap , Shailendra Singh Chauhan , Nagalakshmi Shashidhara Guptha , Nirmala Bailur , Mythili Hegde
发明人: Arvind Sundaram , Santhosh Ap , Shailendra Singh Chauhan , Nagalakshmi Shashidhara Guptha , Nirmala Bailur , Mythili Hegde
IPC分类号: G06F13/42 , G06F1/3296
CPC分类号: G06F1/3296 , G06F13/4282 , G06F2213/0042
摘要: An apparatus can include universal serial bus type C (USB-C) connection circuitry. The apparatus can also include input/output (I/O) circuitry coupled to the USB-C connection circuitry. The I/O circuitry can receive a power signal over the USB-C connection circuitry. The apparatus can include baseband circuitry to initiate wireless wide area network (WWAN) communication responsive to receiving a wake signal from the I/O circuitry. The WWAN communication can include messages received from the USB-C connection circuitry. Other apparatuses, systems, and methods are described.
-
公开(公告)号:US20230409105A1
公开(公告)日:2023-12-21
申请号:US18328301
申请日:2023-06-02
IPC分类号: G06F1/3296 , G06F1/3215
CPC分类号: G06F1/3296 , G06F1/3215
摘要: Embodiments herein relate to avoiding damage to a transistor in a power-sinking device that receives power from an external power source via a Universal Serial Bus port. In one aspect, a controller of the device sets a current limit to a reduced level during a wait period after the external power source is connected to the power-sinking device. The wait period avoids damage to the transistor by allowing its input and output voltages to equalize before the current is increased. Upon expiration of the wait period, the current limit is increased to a level negotiated with the external power source. Other aspects involve considering a sleep or low/dead battery state of the power-sinking device. The current limit can be set by programming a current limit of a battery charger coupled to between the transistor and a power bus of the device.
-
公开(公告)号:US20210326149A1
公开(公告)日:2021-10-21
申请号:US17359512
申请日:2021-06-26
申请人: Arthur Jeremy Runyan , Ratheesh Purushothaman Nair , Shailendra Singh Chauhan , Digant H. Solanki
发明人: Arthur Jeremy Runyan , Ratheesh Purushothaman Nair , Shailendra Singh Chauhan , Digant H. Solanki
IPC分类号: G06F9/4401 , G06F13/40 , G06F1/3218
摘要: Particular embodiments described herein provide for an electronic device that includes two or more displays and a BIOS. On startup, before the premem state and MRC initialization of the boot process, the BIOS causes power to be enabled to two or more displays. A display engine determines if a hot plug for each display is asserted and for each display where the hot plug was not asserted, the path to the display where the hot plug was not asserted is closed. In an example, the BIOS communicates the signal to power enable the first display and the second display after general-purpose input/output initialization during the boot process. After the premem stage and MRC initialization are completed, the first display and the second display are both configured to begin to display pixels.
-
-
-