公开(公告)号：US20200287054A1

公开(公告)日：2020-09-10

申请号：US16808463

申请日：2020-03-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Yoshimasa CHIKAMA ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer positioned between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode that are electrically connected to the semiconductor layer, wherein the semiconductor layer has a stacked layer structure including a first oxide semiconductor layer including In, Ga, Zn, and Sn, and a second oxide semiconductor layer including In, Ga, Zn, and Sn, having a lower mobility than the first oxide semiconductor layer, and disposed on the first oxide semiconductor layer so as to be in direct contact with the first oxide semiconductor layer, the first and the second oxide semiconductor layers are amorphous, and a Sn atomic ratio R1 relative to all metal elements in the first oxide semiconductor layer and a Sn atomic ratio R2 relative to all metal elements in the second oxide semiconductor layer satisfy 0.8×R1≤R2≤1.2×R1.

公开(公告)号：US20210124220A1

公开(公告)日：2021-04-29

申请号：US17075750

申请日：2020-10-21

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshiharu HIRATA ,  Yoshihito HARA ,  Hideki KITAGAWA ,  Tatsuya KAWASAKI ,  Masaki MAEDA ,  Teruyuki UEDA ,  Yoshimasa CHIKAMA ,  Hajime IMAI ,  Tohru DAITOH

IPC: G02F1/1343 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1337 ,  G06F3/041

Abstract: An active matrix substrate includes TFTs, an interlayer insulating layer, a common electrode, a first dielectric layer, pixel electrodes, a second dielectric layer, and touch wirings, in which each of the pixel electrodes at least partially overlaps the common electrode via the first dielectric layer, so that an auxiliary capacitance including each of the pixel electrodes, the common electrode, and the first dielectric layer is formed, the touch sensor electrodes include a first electrode, the touch wirings include a first wiring and a second wiring in the touch sensor electrodes, the second wiring extends to the other electrode across the first electrode when viewed from a normal direction, and a portion of the second wiring overlaps the first electrode via the first and the second dielectric layers, so that a touch wiring capacitance including the second wiring, the first electrode, the first and the second dielectric layers is formed.

公开(公告)号：US20170194359A1

公开(公告)日：2017-07-06

申请号：US15422546

申请日：2017-02-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Yuichi SAITO ,  Yohsuke KANZAKI ,  Yudai TAKANISHI ,  Tetsuya OKAMOTO ,  Yoshiki NAKATANI ,  Yoshimasa CHIKAMA

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4763 ,  H01L21/465 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L27/1225 ,  G02F1/133345 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2001/136295 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/44 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/53233 ,  H01L23/53238 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a circuit board having excellent productivity, particularly a circuit board having excellent productivity with respect to a semiconductor layer and source layer forming step, a display device, and a process for producing a circuit board. The circuit board of the present invention is a circuit board including an oxide semiconductor layer and an electrode connected to the oxide semiconductor layer, wherein the electrode is formed by essentially laminating a layer made of a metal other than copper and a layer containing copper.

公开(公告)号：US20220317532A1

公开(公告)日：2022-10-06

申请号：US17708121

申请日：2022-03-30

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshimasa CHIKAMA ,  Masamitsu YAMANAKA

IPC: G02F1/1362 ,  G02F1/1368

Abstract: A first substrate of a liquid crystal display device includes a plurality of gate wiring lines, a plurality of source wiring lines, a thin film transistor (TFT) provided in each of the pixels, a pixel electrode formed of a transparent conductive material and electrically connected to the TFT, a reflective electrode including a portion positioned in a reflective region, and a terminal portion disposed in a non-display region. The pixel electrode is formed in an upper layer above the reflective electrode, and the reflective electrode is not in contact with the pixel electrode. The terminal portion includes at least one of a first conductive layer formed in a same layer as that of the gate wiring lines and a second conductive layer formed in a same layer as that of the source wiring lines, and a third conductive layer formed in a same layer as that of the pixel electrode, and does not include a conductive layer formed in a same layer as that of the reflective electrode.

公开(公告)号：US20200219903A1

公开(公告)日：2020-07-09

申请号：US16635577

申请日：2018-07-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Ryuji MATSUMOTO ,  Yoshimasa CHIKAMA ,  Hirokazu FURUKAWA

IPC: H01L27/12 ,  H01L21/311

Abstract: A substrate of the present invention sequentially includes an insulating substrate, a lower layer, a first insulating film, a second insulating film, and an upper layer. The substrate is provided with a hole reaching at least one of the lower layer or the insulating substrate through at least the first insulating film and the second insulating film. The first insulating film includes in a region with the hole a protrusion that protrudes from an end portion in contact with the first insulating film of the second insulating film. The substrate includes a stepwise structure including the protrusion and the end portion. The upper layer coats the stepwise structure. An upper surface portion of the first insulating film in a region with the protrusion and an upper surface portion of the first insulating film in a region below the end portion of the second insulating film are coplanar.

公开(公告)号：US20220005838A1

公开(公告)日：2022-01-06

申请号：US17364938

申请日：2021-07-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Masamitsu YAMANAKA ,  Yoshimasa CHIKAMA

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on a part of the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, the oxide semiconductor layer, in a first region covered with the gate electrode with the gate insulating layer interposed between the oxide semiconductor layer and the gate electrode, has a layered structure including a lower oxide semiconductor film and an upper oxide semiconductor film throughout and a mobility of the upper oxide semiconductor film is higher than a mobility of the lower oxide semiconductor film, and in the second TFT, in at least a part of a first region of the oxide semiconductor layer, of the lower oxide semiconductor film and the upper oxide semiconductor film, one oxide semiconductor film is provided, and another oxide semiconductor film is not provided.

公开(公告)号：US20190221590A1

公开(公告)日：2019-07-18

申请号：US16329784

申请日：2017-08-31

Applicant: Sharp Kabushiki Kaisha

Inventor： Jun NISHIMURA ,  Yoshihito HARA ,  Yoshimasa CHIKAMA ,  Yukinobu NAKATA

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1368

Abstract: Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection circuit (200) that includes multiple inspection TFTs (10Q). At least one or more of the multiple inspection TFTs (10Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (10Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.

公开(公告)号：US20140367683A1

公开(公告)日：2014-12-18

申请号：US14478055

申请日：2014-09-05

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshifumi OHTA ,  Go MORI ,  Hirohiko NISHIKI ,  Yoshimasa CHIKAMA ,  Tetsuya AITA ,  Masahiko SUZUKI ,  Okifumi NAKAGAWA ,  Michiko TAKEI ,  Yoshiyuki HARUMOTO ,  Takeshi HARA

IPC: H01L29/22 ,  H01L29/786

CPC classification number: H01L29/22 ,  G02F1/1368 ,  G02F2202/10 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.

Abstract translation: 本发明提供一种能够实现具有稳定晶体管特性的薄膜晶体管的氧化物半导体，具有由氧化物半导体形成的沟道层的薄膜晶体管及其制造方法，以及配备有该薄膜晶体管的显示装置。 本发明的氧化物半导体是薄膜晶体管的氧化物半导体。 氧化物半导体包括铟，镓，锌和氧作为构成原子，并且氧化物半导体的氧含量为化学计量条件的87％至95％，以原子单位计为100％。