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公开(公告)号：US10825414B2
公开(公告)日：2020-11-03
申请号：US16659681
申请日：2019-10-22
Applicant: Sharp Kabushiki Kaisha
Inventor： Kohhei Tanaka , Takuya Watanabe , Yasuaki Iwase
IPC: G09G3/36
Abstract: An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.
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公开(公告)号：US10473958B2
公开(公告)日：2019-11-12
申请号：US15511427
申请日：2015-09-17
Applicant: Sharp Kabushiki Kaisha
Inventor： Yasuaki Iwase , Takuya Watanabe
Abstract: The present invention provides a monolithic gate driver that includes fewer elements than in conventional configurations. In one aspect, a plurality of stages included in a shift register are divided into a plurality of stage circuit groups, where each stage circuit group includes the stage circuits of P adjacent stages (two stages, for example). Each stage circuit group includes a stabilization node and a stabilization node controller that controls the voltage of the stabilization node. The stabilization node controller includes: thin-film transistors in which the gate terminals thereof are connected to output control nodes, the drain terminals thereof are connected to the stabilization node, and the source terminals thereof are connected to an input terminal for a DC supply voltage; and a thin-film transistor for changing the voltage of the stabilization node to a high level.
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公开(公告)号：US10984747B2
公开(公告)日：2021-04-20
申请号：US16935238
申请日：2020-07-22
Applicant: Sharp Kabushiki Kaisha
Inventor： Akira Tagawa , Takuya Watanabe , Jun Nishimura , Yasuaki Iwase , Yohei Takeuchi
IPC: G09G3/36
Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.
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公开(公告)号：US10923064B2
公开(公告)日：2021-02-16
申请号：US16500427
申请日：2018-04-10
Applicant: Sharp Kabushiki Kaisha
Inventor： Yohei Takeuchi , Takuya Watanabe , Yasuaki Iwase , Akira Tagawa
Abstract: A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.
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公开(公告)号：US10657917B2
公开(公告)日：2020-05-19
申请号：US15767510
申请日：2016-10-12
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Toshitsugu Sueki , Yasuaki Iwase , Takuya Watanabe
Abstract: A shift register is implemented that can increase the reliability of long-term operation regarding the driving of gate bus lines over a conventional configuration. The shift register is allowed to operate by clock signals of eight or more phases with an on-duty of less than ½. A stabilization node control portion brings a stabilization node (NB) to an on level for a period less than 50 percent of a normal operation period, based on two or more clock signals among the clock signals of eight or more phases, the stabilization node (NB) being connected to a gate terminal of a thin film transistor that contributes to the drawing of a potential of an output control node (NA) to a VSS potential.
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Patent Agency Ranking
公开(公告)号：US10902813B2
公开(公告)日：2021-01-26
申请号：US16191234
申请日：2018-11-14
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Yohei Takeuchi , Takuya Watanabe , Akira Tagawa , Yasuaki Iwase , Takatsugu Kusumi
Abstract: Each unit circuit that constitutes each of stages of a shift register is provided with a charge supply unit including a third node whose potential becomes high level at identical timing with a first node (a node for holding an electric charge in order to output a scanning signal (output signal) at high level), and capable of supplying an electric charge to the first node throughout a period after the potential of the third node becomes high level until the scanning signal (output signal) at high level is outputted. Here, all of the unit circuits within the shift register have an identical configuration.
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公开(公告)号：US10854163B2
公开(公告)日：2020-12-01
申请号：US16592808
申请日：2019-10-04
Applicant: Sharp Kabushiki Kaisha
Inventor： Jun Nishimura , Takuya Watanabe
IPC: G09G3/36
Abstract: When supply of power has stopped, voltages of GDM signals are set as follows. A clear signal that contributes to removal of charge at floating nodes (an output control node and a stabilization node) in each unit circuit included in a shift register is set to a voltage of ground, and other signals (a gate start pulse signal, gate clock signals, and a reference voltage) are set to a gate-on voltage. To implement such settings, a single power supply system configuration that uses a voltage of only one channel as a scanning line selection voltage is adopted.
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公开(公告)号：US10818260B2
公开(公告)日：2020-10-27
申请号：US16191226
申请日：2018-11-14
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Akira Tagawa , Takuya Watanabe , Yasuaki Iwase , Takatsugu Kusumi , Yohei Takeuchi
Abstract: Each unit circuit includes a thin film transistor (first stabilization transistor) having a gate terminal to which a clear signal which goes to an on level when a frame period ends applied, a drain terminal connected to a charge holding node, and a source terminal to which a potential of an off level is applied. Here, a gate length of the thin film transistor is set to be larger than gate lengths of other charge holding node turn-off transistors. Alternatively, a multi-gate structure is adopted for the thin film transistor and a single gate structure is adopted for the other charge holding node turn-off transistors.
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公开(公告)号：US10796655B2
公开(公告)日：2020-10-06
申请号：US16234347
申请日：2018-12-27
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Takatsugu Kusumi , Takuya Watanabe , Akira Tagawa , Yasuaki Iwase , Yohei Takeuchi
IPC: G09G3/36 , G02F1/1368 , H01L27/12
Abstract: A configuration in which a voltage (a gate on voltage) of only one system is used as a voltage for turning scanning lines to a selected state is employed (single power supply system configuration). A unit circuit that constitutes a shift register within a gate driver includes a thin film transistor whose source terminal is connected to an output control node. In such a configuration, when the external power supply is stopped, a voltage supplied to a gate terminal of the thin film transistor and a voltage supplied to a drain terminal of the thin film transistor are set to the gate on voltage.
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公开(公告)号：US10777111B2
公开(公告)日：2020-09-15
申请号：US16387324
申请日：2019-04-17
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Yohei Takeuchi , Takuya Watanabe , Akira Tagawa , Yasuaki Iwase , Takatsugu Kusumi
IPC: G09G3/02 , G09G3/36 , G02F1/1343 , G02F1/1362
Abstract: A plurality of pixel formation portions in an image display portion are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more. The K pixel formation portions forming each of the pixel groups are connected to the same source bus line. Each of the pixel formation portions is provided with a connection control transistor configured to control an electrical connection state between the corresponding source bus line and a pixel electrode. The K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another. A source driver applies a video signal to each of the source bus lines in a time division manner in each horizontal scanning period.
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