公开(公告)号：US20050008110A1

公开(公告)日：2005-01-13

申请号：US10604296

申请日：2003-07-09

申请人： Sheehan Lake ,  David Stauffer

发明人： Sheehan Lake ,  David Stauffer

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033

CPC分类号： H04L7/02 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0337 ,  H04L7/0338

摘要： A system and method for aligning data transferred across circuit boundaries having different clock domains. The system includes a buffer circuit comprising a latch for receiving data clocked in a first clock domain and latching the received data in a second clock domain by one of a first edge of a second clock signal, or a second opposite edge of the second clock signal. The first and second clock signals are of the same frequency but operating out of phase. A control circuit receives the first and second clock signals and determines a phase relationship therebetween. The control circuit generates a control signal based on the determined phase relationship which is implemented for selecting one of a rising edge of the second clock signal, or a falling edge of the second clock signal, for latching action in the second clock domain. Reliable data transfer operation is provided for all possible phase relationships of the first and second clock signals.

摘要翻译： 用于对准跨越具有不同时钟域的电路边界传输的数据的系统和方法。 该系统包括缓冲电路，该缓冲电路包括用于接收以第一时钟域计时的数据的锁存器，并且通过第二时钟信号的第一边缘或第二时钟信号的第二相对边沿将第二时钟域中的接收数据锁存在第二时钟域中 。 第一和第二时钟信号的频率相同，但是不同相位。 控制电路接收第一和第二时钟信号并确定它们之间的相位关系。 控制电路基于所确定的相位关系产生控制信号，该相位关系用于选择第二时钟信号的上升沿或第二时钟信号的下降沿中的一个，用于在第二时钟域中进行锁存动作。 为第一和第二时钟信号的所有可能的相位关系提供可靠的数据传送操作。