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1.发明申请公开(公告)号：US20100135271A1
公开(公告)日：2010-06-03
申请号：US12704439
申请日：2010-02-11
申请人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
发明人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.
摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。
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2.发明授权公开(公告)号：US08169990B2
公开(公告)日：2012-05-01
申请号：US13118115
申请日：2011-05-27
申请人： Sherman Lee , Vivian Chou , Charles T. Aragones , John Lin
发明人： Sherman Lee , Vivian Chou , Charles T. Aragones , John Lin
IPC分类号： H04W84/02
摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.
摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以保持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。
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3.发明授权公开(公告)号：US07411934B2
公开(公告)日：2008-08-12
申请号：US10293111
申请日：2002-11-13
申请人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
发明人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
IPC分类号： H04Q7/24
摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.
摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。
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公开(公告)号：US20050010745A1
公开(公告)日：2005-01-13
申请号：US10914105
申请日：2004-08-09
申请人： Sherman Lee , Vivian Chou , John Lin
发明人： Sherman Lee , Vivian Chou , John Lin
摘要： A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.
摘要翻译： 一种包括具有编程微码的只读存储器（ROM）和能够存储微代码的随机存取存储器（RAM）和用于选择相应的ROM或RAM微代码以用于执行的一个或多个数据位的微处理器存储器架构。 多路复用器从ROM微码和RAM微码接收输入信号，并且使用作为一个或多个RAM数据位的控制信号从RAM或ROM微码输入中进行选择以供微处理器进一步执行。
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5.发明申请公开(公告)号：US20110228754A1
公开(公告)日：2011-09-22
申请号：US13118115
申请日：2011-05-27
申请人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
发明人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
IPC分类号： H04W84/02
摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.
摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。
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公开(公告)号：US20070202827A1
公开(公告)日：2007-08-30
申请号：US11796837
申请日：2007-04-30
申请人： Sherman Lee , Vivian Chou , John Lin
发明人： Sherman Lee , Vivian Chou , John Lin
IPC分类号： H04B1/06
CPC分类号： G06F9/328 , G06F8/66 , G06F9/268 , H04B1/7156 , H04B2001/71566 , H04J3/062 , H04L25/05 , H04W84/18 , H04W88/02
摘要： A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.
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公开(公告)号：US20060101164A1
公开(公告)日：2006-05-11
申请号：US11314036
申请日：2005-12-20
申请人： Sherman Lee , Vivian Chou , John Lin
发明人： Sherman Lee , Vivian Chou , John Lin
IPC分类号： G06F3/00
CPC分类号： G06F9/462
摘要： A method and system for performing switch operations utilize non-architectural registers to store context information. Data in a first context register on a peripheral system is accessed (e.g., read or write) until a host computer provides a new index value to an index register on the peripheral system. A context switch occurs, and the context register associated with the new index value is accessed. In some embodiments a system that performs context switching includes a host computer, at least one peripheral system coupled to the host computer, an interface between the host computer and the peripheral system, and a register access circuit coupled to the host computer. The register access circuit is configured to access data in a first or a second register on the peripheral system if the first or a second index value, respectively, is provided by the host computer.
摘要翻译： 用于执行切换操作的方法和系统利用非架构寄存器来存储上下文信息。 在外围系统上的第一上下文寄存器中的数据被访问（例如，读取或写入），直到主计算机向外围系统上的索引寄存器提供新的索引值。 发生上下文切换，并且访问与新索引值相关联的上下文寄存器。 在一些实施例中，执行上下文切换的系统包括主计算机，耦合到主计算机的至少一个外围系统，主计算机和外围系统之间的接口以及耦合到主计算机的寄存器访问电路。 寄存器访问电路被配置为如果分别由主计算机提供第一或第二索引值，则访问外围系统上的第一或第二寄存器中的数据。
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8.发明授权公开(公告)号：US07953057B2
公开(公告)日：2011-05-31
申请号：US12704439
申请日：2010-02-11
申请人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
发明人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
IPC分类号： H04W40/00
摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.
摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。
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9.发明授权公开(公告)号：US07684377B2
公开(公告)日：2010-03-23
申请号：US12174629
申请日：2008-07-16
申请人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
发明人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
IPC分类号： H04Q7/24
摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.
摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。
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10.发明申请公开(公告)号：US20080273508A1
公开(公告)日：2008-11-06
申请号：US12174629
申请日：2008-07-16
申请人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
发明人： Sherman Lee , Vivian Chou , Charles Aragones , John Lin
摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.
摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。
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