利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

70 条记录 (耗时 0.025 秒)

    Packetized audio data operations in a wireless local area network device
    1.
    发明授权
    Packetized audio data operations in a wireless local area network device 有权
    无线局域网设备中的分组化音频数据操作

    公开(公告)号：US07411934B2

    公开(公告)日：2008-08-12

    申请号：US10293111

    申请日：2002-11-13

    申请人： Sherman Lee ,  Vivian Chou ,  Charles Aragones ,  John Lin

    发明人： Sherman Lee ,  Vivian Chou ,  Charles Aragones ,  John Lin

    IPC分类号： H04Q7/24

    CPC分类号： H04W88/06 ,  H04W28/14 ,  H04W84/12

    摘要： A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.

    摘要翻译： 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。

    Wireless data communications using FIFO for synchronization memory
    2.
    发明授权
    Wireless data communications using FIFO for synchronization memory 失效
    无线数据通信使用FIFO进行同步存储

    公开(公告)号：US07167727B2

    公开(公告)日：2007-01-23

    申请号：US10674693

    申请日：2003-09-30

    申请人： Sherman Lee ,  Vivian Y. Chou ,  John H. Lin

    发明人： Sherman Lee ,  Vivian Y. Chou ,  John H. Lin

    IPC分类号： H04B1/38

    CPC分类号： G06F9/328 ,  G06F8/66 ,  G06F9/268 ,  H04B1/7156 ,  H04B2001/71566 ,  H04J3/062 ,  H04L25/05 ,  H04W84/18 ,  H04W88/02

    摘要： A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

    摘要翻译： 无线（Radio）接收机接收携带与第一时钟同步的数据的RF信号。 无线接收机解调RF信号以提取数据信号和第一时钟信号。 无线接收机使用第一时钟信号作为写入信号，以先进先出的存储器件（FIFO）来写入数据信号。 存储在FIFO中的数据信号可以用与第二时钟同步的读取信号读出。 在一个示例中，与无线接收器相关联的主机以与主机接收机的系统时钟同步的读取信号读出存储在FIFO中的数据信号。 在另一示例中，无线接收器包括数据处理电路（例如，包括前向纠错，去白化和循环冗余校验电路），其读出存储在FIFO中的数据信号，其中读取信号与无线系统时钟同步 接收器。 公开了一种微处理器系统架构，其允许选择性地执行编程的ROM微代码，或者替代地，如果已经对最初编程到系统中的ROM微代码进行了校正或更新，则可以选择性地执行RAM微代码。 修补或更新的RAM微代码仅在ROM微代码的改变程度上被使用或执行，否则ROM微代码以其正常方式执行。 当接收到补丁时，它将与指令或其他适当的信号一起加载到系统RAM中，以指导来自RAM的修补或更新的微代码的执行，而不是现有的ROM微代码。 呈现各种方法用于根据是否对其进行了改变来选择适当的微代码的执行。

    Dynamic field patchable microarchitecture
    4.
    发明申请
    Dynamic field patchable microarchitecture 有权
    动态现场可拼接微架构

    公开(公告)号：US20050010745A1

    公开(公告)日：2005-01-13

    申请号：US10914105

    申请日：2004-08-09

    申请人： Sherman Lee ,  Vivian Chou ,  John Lin

    发明人： Sherman Lee ,  Vivian Chou ,  John Lin

    IPC分类号： G06F9/24 ,  G06F9/26 ,  G06F9/445 ,  H04B7/26 ,  H04J3/06 ,  H04L25/05 ,  G06F9/30

    CPC分类号： H04L25/05 ,  G06F8/66 ,  G06F9/24 ,  G06F9/268 ,  G06F9/328 ,  H04B7/2662 ,  H04J3/062

    摘要： A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.

    摘要翻译： 一种包括具有编程微码的只读存储器（ROM）和能够存储微代码的随机存取存储器（RAM）和用于选择相应的ROM或RAM微代码以用于执行的一个或多个数据位的微处理器存储器架构。 多路复用器从ROM微码和RAM微码接收输入信号，并且使用作为一个或多个RAM数据位的控制信号从RAM或ROM微码输入中进行选择以供微处理器进一步执行。

    Method and system for fast data transmissions in a processing system utilizing interrupts
    5.
    发明授权
    Method and system for fast data transmissions in a processing system utilizing interrupts 失效
    在利用中断的处理系统中快速数据传输的方法和系统

    公开(公告)号：US5923852A

    公开(公告)日：1999-07-13

    申请号：US708308

    申请日：1996-09-04

    申请人： Sherman Lee ,  Ramkrishna Vepa ,  Robert Alan Williams

    发明人： Sherman Lee ,  Ramkrishna Vepa ,  Robert Alan Williams

    IPC分类号： G06F13/00 ,  H04L12/56 ,  H04L13/08 ,  G06F17/00

    CPC分类号： H04L49/901 ,  H04L49/90

    摘要： A system and method for facilitates a fast transmission of packet information into the buffers without unnecessary delays, thereby increasing overall system performance. The method and system comprises sending a packet of information located in a local buffer to a media, generating an interrupt signal indicating a completed transfer of the packet to the media and availability of the local buffer for receiving a next packet, and sending the next packet of information from a queue to the local buffer in response to the interrupt signal, wherein the generation of the interrupt signal after each data packet is transmitted to the media does not affect the overall operation of the processing system.

    摘要翻译： 一种用于促进将分组信息快速传输到缓冲器而不需要不必要的延迟的系统和方法，从而提高整个系统性能。 所述方法和系统包括将位于本地缓冲器中的信息分组发送到媒体，产生指示分组到媒体的完整传送的中断信号以及用于接收下一分组的本地缓冲器的可用性，以及发送下一分组 响应于中断信号从队列到本地缓冲器的信息，其中在每个数据分组被发送到媒体之后生成中断信号不影响处理系统的整体操作。

    Method and system for detection of and graceful recovery from a peripheral device fault
    6.
    发明授权
    Method and system for detection of and graceful recovery from a peripheral device fault 失效
    从外围设备故障检测和正常恢复的方法和系统

    公开(公告)号：US5805791A

    公开(公告)日：1998-09-08

    申请号：US635845

    申请日：1996-04-22

    申请人： Leonid Grossman ,  Sherman Lee ,  Ramkrishna Vepa

    发明人： Leonid Grossman ,  Sherman Lee ,  Ramkrishna Vepa

    IPC分类号： G06F11/14 ,  G06F11/00

    CPC分类号： G06F11/142

    摘要： A system and method for detecting and gracefully recovering from a peripheral device fault has been disclosed. The method detects whether a peripheral device has suffered from a peripheral device fault. Where the peripheral device fault has occurred, the method determines whether any of a plurality of processes executable by the peripheral device is currently being executed by the peripheral device. The plurality of processes comprises those process which could result in significant loss of data, loss of connection to a network or adversely affect the performance of the peripheral device if the peripheral device is reset during execution of any of the plurality of processes. If none of the plurality of processes is being executed by the peripheral device, the method automatically resets the peripheral device. According to the method and system disclosed, peripheral devices can be made to recover from faults without user intervention, without loss of connection to any networks, and with minimal loss of data. Reliability is improved, thereby increasing overall system performance.

    摘要翻译： 已经公开了一种用于从外围设备故障检测和正常恢复的系统和方法。 该方法检测外围设备是否遭受外围设备故障。 在发生外围设备故障的情况下，该方法确定外围设备当前是否正在执行由外围设备执行的多个进程中的任何一个。 多个处理包括那些可能导致数据显着丢失，丢失与网络的连接或不利地影响外围设备的性能的过程，如果外围设备在多个进程中的任何一个执行期间被复位。 如果外围设备没有执行多个处理，则该方法自动复位外围设备。 根据所公开的方法和系统，可以使外围设备在没有用户干预的情况下从故障中恢复，而不损失与任何网络的连接，并且以最小的数据丢失。 可靠性得到提高，从而提高整体系统性能。

    Swivel base apparatus and method of making a swivel base
    9.
    发明授权
    Swivel base apparatus and method of making a swivel base 失效
    旋转基座装置及旋转底座的制造方法

    公开(公告)号：US5685514A

    公开(公告)日：1997-11-11

    申请号：US512415

    申请日：1995-08-08

    申请人： Garnett Carnahan ,  Caroline Carnahan ,  Sherman Lee

    发明人： Garnett Carnahan ,  Caroline Carnahan ,  Sherman Lee

    IPC分类号： A47B11/00 ,  A47C3/18 ,  F16M11/08 ,  F16M13/00

    CPC分类号： F16M11/08 ,  A47B11/00 ,  A47C3/18 ,  F16M2200/08

    摘要： An apparatus which includes a swivel base formed of a first plate and a second plate. The first and second plates each have a central aperture which is defined by a hook-shaped section of the second plate which extends over an interior edge of the first plate defining the first plate's central aperture. The hook-shaped section is preferably circumferentially continuous and fixes the first and second plates together while allowing for sliding engagement between the first and second plates. Bearing members, such as circumferentially spaced ball bearings are provided externally to the hook section and between the plates to facilitate sliding and load distribution. One of the plates includes hollow reception ports for holding the bearing circumferentially in place with respect to that plate while the opposite plate has a continuous riding ring in which the bearings are free to rotate. Each plate has an interior and exterior, preferably horizontal, plate section, and an intermediate section sloping between the adjacent, integral edges of the plate's interior and exterior sections. One manner of assembling the swivel base is described as well as an assembly including two structures to which the exterior sections of the plates are secured.

    摘要翻译： 一种装置，包括由第一板和第二板形成的旋转底座。 第一和第二板各自具有中心孔，该中心孔由第二板的钩形部分限定，其在限定第一板的中心孔的第一板的内部边缘上延伸。 钩形部分优选是周向连续的，并且将第一和第二板固定在一起，同时允许第一和第二板之间的滑动接合。 诸如周向隔开的球轴承之类的轴承构件设置在钩部分的外部和板之间，以便于滑动和载荷分布。 其中一个板包括中空的接收端口，用于将轴承相对于板保持在周向就位，而相对的板具有连续的骑行环，轴承可自由转动。 每个板具有内部和外部，优选水平的板部分，以及在板的内部和外部部分的相邻的整体边缘之间倾斜的中间部分。 描述组装旋转底座的一种方式以及包括两个结构件的组件，板的外部部分固定到该组件上。

    System and method for enabling and disabling a clock run function to control a peripheral bus clock signal
    10.
    发明授权
    System and method for enabling and disabling a clock run function to control a peripheral bus clock signal 失效
    用于启用和禁用时钟运行功能以控制外设总线时钟信号的系统和方法

    公开(公告)号：US5625807A

    公开(公告)日：1997-04-29

    申请号：US308596

    申请日：1994-09-19

    申请人： Sherman Lee ,  Michael T. Wisor

    发明人： Sherman Lee ,  Michael T. Wisor

    IPC分类号： G06F13/36 ,  G06F1/32 ,  G06F1/08

    CPC分类号： G06F1/3215 ,  G06F1/325

    摘要： A system and method for controlling a peripheral bus clock signal through a master and/or slave device is provided that accommodates a power conservation (or "clock run") scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. The clock run feature is enabled or disabled by the system during or immediately following system initialization, based upon the ability of the peripheral bus components to support the clock run feature. The system includes status and command registers to provide an indication of whether each of the peripheral bus devices can support the power conservation scheme. The status and command registers both include a bit dedicated to the clock run function. The status register bit is set based upon whether that particular device can support the clock run function. After each of the dedicated status register bits is checked, the dedicated command register bit is set in each of the peripheral bus devices to either enable or disable the clock run feature.

    摘要翻译： 提供了一种用于通过主设备和/或从设备控制外围总线时钟信号的系统和方法，其适应功率节省（或“时钟运行”）方案，其中可以停止外部总线时钟信号，例如通过 电源管理单元或其他中央资源。 基于外设总线组件支持时钟运行功能的能力，系统在系统初始化期间或之后系统启用或禁用时钟运行功能。 该系统包括状态和命令寄存器，以提供每个外围总线设备是否能够支持功率节省方案的指示。 状态和命令寄存器都包含专用于时钟运行功能的位。 基于该特定设备是否可以支持时钟运行功能来设置状态寄存器位。 在检查每个专用状态寄存器位之后，在每个外设总线器件中设置专用命令寄存器位，以使能或禁止时钟运行特性。