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    Programmable counter/timer device with programmable registers having programmable functions
    2.
    发明授权
    Programmable counter/timer device with programmable registers having programmable functions 失效
    具有可编程功能的可编程寄存器的可编程计数器/定时器器件

    公开(公告)号：US5089955A

    公开(公告)日：1992-02-18

    申请号：US484909

    申请日：1990-02-26

    申请人： Shigeki Morinaga ,  Mitsuru Watabe

    发明人： Shigeki Morinaga ,  Mitsuru Watabe

    IPC分类号： G04G15/00 ,  G04G99/00

    CPC分类号： G04G99/006 ,  G04G15/006

    摘要： A counter timer device includes a plurality of registers each capable of performing any of the function of a counter/timer register, the function of a capture register and the function of a compare register, in accordance with a command from a central processing unit, and a plurality of task registers corresponding to tasks which are to be carried out by using the above registers. Each of the task registers stores a task instruction for specifying a counter/timer register and a capture/compare register which are used in a task, and for specifying the operation mode of each of the specified registers. The task registers are scanned to successively read out the task instructions, and each of the read-out task instructions controls the operation of each of registers used in a corresponding task. Thus, tasks corresponding to the task instructions are all carried out at once.

    摘要翻译： 计数器定时器装置包括多个寄存器，每个寄存器能够根据来自中央处理单元的命令执行计数器/定时器寄存器的功能，捕获寄存器的功能和比较寄存器的功能，以及 对应于将通过使用上述寄存器执行的任务的多个任务寄存器。 每个任务寄存器存储用于指定在任务中使用的计数器/定时器寄存器和捕获/比较寄存器的任务指令，以及用于指定每个指定寄存器的操作模式。 扫描任务寄存器以连续读取任务指令，并且每个读出任务指令控制在相应任务中使用的每个寄存器的操作。 因此，与任务指令相对应的任务都是一次执行的。

    Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system
    3.
    发明授权
    Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system 失效
    用于控制处理器系统中的保存和恢复操作的执行时序的方法和装置

    公开(公告)号：US5642499A

    公开(公告)日：1997-06-24

    申请号：US223834

    申请日：1994-04-06

    申请人： Mamoru Ohba ,  Shigeki Morinaga ,  Mitsuru Watabe ,  Hiroyuki Kida

    发明人： Mamoru Ohba ,  Shigeki Morinaga ,  Mitsuru Watabe ,  Hiroyuki Kida

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F11/28 ,  G06F15/16 ,  G06F15/177

    CPC分类号： G06F9/461 ,  G06F9/30025 ,  G06F9/3861 ,  G06F9/3885

    摘要： In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.

    摘要翻译： 在具有中央处理单元（CPU）的协处理器系统中，当CPU向FPU发出保存命令时，通过总线彼此耦合的浮点处理单元（FPU）和存储器（RAM），FPU鉴别 FPU在接收到保存命令及其内部状态时执行的当前命令的属性，即长命令或短命令。 响应于鉴别结果，FPU一旦中断当前命令的执行，开始执行接收到的保存命令，当前命令为长命令，并且FPU在执行完成后执行接收到的保存命令 的当前命令，如果当前命令是一个短命令。 基于执行命令所需的时间和为此提供的预定标准，预先确定命令的属性。

    Analog-digital converting device
    4.
    发明授权
    Analog-digital converting device 失效
    模拟数字转换器

    公开(公告)号：US5349351A

    公开(公告)日：1994-09-20

    申请号：US940332

    申请日：1992-09-03

    申请人： Sanshiro Obara ,  Mitsuru Watabe ,  Rika Minami ,  Shigeki Morinaga

    发明人： Sanshiro Obara ,  Mitsuru Watabe ,  Rika Minami ,  Shigeki Morinaga

    IPC分类号： G01R19/00 ,  G06F15/78 ,  H02M7/48 ,  H03M1/12 ,  G05B11/28

    CPC分类号： H03M1/1225

    摘要： An analog-digital converting device is designed such that when an operation of converting a special analog signal into a digital signal and an operation of converting another analog signal into a digital signal are instructed concurrently, priority is given to the conversion operation of the special analog signal, The analog-digital converting device includes an analog multiplexer having a main channel and a sub channel, a sample holder, an AD converter, a conversion result register having a plurality of storage areas, and an AD control circuit for controlling the drive of the individual components according to an instruction of a CPU. When the analog signals input to the channels are converted into digital signals in sequence, priority is given to AD conversion of the analog signal input to the main channel over AD conversion of the analog signal input to the sub channel.

    摘要翻译： 模拟数字转换装置被设计成当同时指示将特殊模拟信号转换为数字信号的操作和将另一个模拟信号转换为数字信号的操作时，优先考虑特殊模拟信号的转换操作 模拟数字转换装置包括具有主信道和子信道的模拟多路复用器，样本保持器，AD转换器，具有多个存储区域的转换结果寄存器，以及用于控制驱动器的AD控制电路 各个组件根据CPU的指令。 当输入到通道的模拟信号按顺序转换为数字信号时，通过AD转换将模拟信号输入到主通道的模拟信号的AD转换优先给输入到子通道。

    Position/speed detection method and apparatus
    8.
    发明授权
    Position/speed detection method and apparatus 失效
    位置/速度检测方法和装置

    公开(公告)号：US4922175A

    公开(公告)日：1990-05-01

    申请号：US318688

    申请日：1989-03-03

    申请人： Yasuyuki Sugiura ,  Mitsuru Watabe ,  Shigeki Morinaga ,  Kunio Miyashita ,  Hiroshi Sugai

    发明人： Yasuyuki Sugiura ,  Mitsuru Watabe ,  Shigeki Morinaga ,  Kunio Miyashita ,  Hiroshi Sugai

    IPC分类号： G01D5/245 ,  G01D5/244

    CPC分类号： G01D5/24409

    摘要： Disclosed is a position detecting method and apparatus which are suitable for detecting the position of a moving body on the basis of the output of a position detector for generating two-phase periodic waves having a phase difference of a quarter period, the method comprising the steps of: comparing either one of the two-phase periodic waves with a predetermined reference value having hysteresis to thereby obtain a roughly estimated position for every half period of the one periodic wave; analog-to-digital converting the two-phase periodic waves and a zero-cross value for every sampling period to thereby obtain a finely estimated position; and detecting the position of the moving body on the basis of the roughly estimated position and the finely estimated position while correcting an error due to the hysteresis at the starting point of the roughly estimated position, by use of the relationship between the roughly estimated position and the finely estimated position. According to this method/apparatus, continuity between the roughly estimated position and the finely estimated position can be maintained, so that exact and high-resolution position detection can be performed.

    摘要翻译： 公开了一种位置检测方法和装置，其适用于根据用于产生具有四分之一周期的相位差的两相周期波的位置检测器的输出来检测移动体的位置，该方法包括步骤 ：将两相周期波中的任一个与具有滞后的预定参考值进行比较，从而获得一个周期波的每半个周期的粗略估计位置; 在每个采样周期对模拟数字转换两相周期波和零交叉值，从而获得精细估计的位置; 并且通过使用粗略估计位置与粗略估计位置之间的关系，在粗略估计位置和精确估计位置的基础上检测移动体的位置，同时校正由于在粗略估计位置的起点处的滞后导致的误差 精细估计的位置。 根据该方法/装置，能够维持粗略估计位置与精细估计位置之间的连续性，从而能够进行精确，高分辨率的位置检测。

    Generation of width modulated pulses by relatively adjusting rising and falling edges upon comparison of counter with programmably stored values
    10.
    发明授权
    Generation of width modulated pulses by relatively adjusting rising and falling edges upon comparison of counter with programmably stored values 失效
    通过在计数器与可编程存储的值进行比较时相对调整上升沿和下降沿来产生宽度调制脉冲

    公开(公告)号：US5418932A

    公开(公告)日：1995-05-23

    申请号：US649861

    申请日：1991-02-01

    申请人： Mitsuru Watabe ,  Sanshiro Obara ,  Rika Oue ,  Shigeki Morinaga

    发明人： Mitsuru Watabe ,  Sanshiro Obara ,  Rika Oue ,  Shigeki Morinaga

    IPC分类号： G06F1/025 ,  H03K3/017

    CPC分类号： G06F1/025

    摘要： A pulse generating device according to the present invention is operated in accordance with a pulse control command including output time data about output pulse given from external equipment such as a CPU. The pulse control command including the output time data about the output pulses is transferred to a master memory of a contents addressable memory at an optional timing from outside. The contents of that master memory are copied to a slave memory in response to copy enable signals transmitted from a copy enable device. The copy enable signals are transmitted whenever a predetermined number synchronizing signals showing an end of the pulse period are generated from the interval timer. The contents addressable memory reads out the output control command of the output pulse from a slave memory when the timer value of the interval timer coincides with the time data of the slave memory. The output control circuit transmits output pulses which correspond to the control command read out as described above. As a result, if the output time data is reloaded at an optional timing from outside, the generation of an error in the pulse width of the output pulse can be prevented. Furthermore, the load of the CPU can be reduced.

    摘要翻译： 根据本发明的脉冲发生装置根据包括从诸如CPU的外部设备给出的关于输出脉冲的输出时间数据的脉冲控制命令进行操作。 包括关于输出脉冲的输出时间数据的脉冲控制命令从外部以可选定时传送到内容可寻址存储器的主存储器。 响应于从复制使能设备发送的复制使能信号，该主存储器的内容被复制到从存储器。 每当从间隔定时器产生表示脉冲周期结束的预定数量的同步信号时，发送复制使能信号。 内容可寻址存储器当间隔定时器的定时器值与从存储器的时间数据一致时，从从器件读出输出脉冲的输出控制命令。 如上所述，输出控制电路传输与读出的控制命令对应的输出脉冲。 结果，如果从外部以可选定时重新加载输出时间数据，则可以防止产生输出脉冲的脉冲宽度的误差。 此外，可以减少CPU的负载。