公开(公告)号：US5088031A

公开(公告)日：1992-02-11

申请号：US827607

申请日：1986-02-10

申请人： Shigeo Takasaki ,  Masaichiro Yoshioka ,  Takashige Kubo ,  Yoshio Ukai ,  Yasuo Kubo ,  Jinichi Imura ,  Nobutaka Hagiwara

发明人： Shigeo Takasaki ,  Masaichiro Yoshioka ,  Takashige Kubo ,  Yoshio Ukai ,  Yasuo Kubo ,  Jinichi Imura ,  Nobutaka Hagiwara

IPC分类号： G06F12/00 ,  G06F17/30

CPC分类号： G06F17/30067

摘要： A file control system for virtual machines capable of executing simultaneously a plurality of operating systems in a single computer system under control of a virtual machine monitor for controlling the operating systems, wherein interface means for file input/output operation are provided between the virtual machine monitor and the operating systems for allowing the virtual machine monitor to manage a plurality of files owned by the virtual machines.

摘要翻译： 一种用于虚拟机的文件控制系统，其能够在用于控制操作系统的虚拟机监视器的控制下同时执行单个计算机系统中的多个操作系统，其中在虚拟机监视器之间提供用于文件输入/输出操作的接口装置 以及用于允许虚拟机监视器管理虚拟机所拥有的多个文件的操作系统。

公开(公告)号：US5109489A

公开(公告)日：1992-04-28

申请号：US369535

申请日：1989-06-21

申请人： Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto

发明人： Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F12/08 ,  G06F12/10 ,  G06F13/10

CPC分类号： G06F13/10 ,  G06F9/45558 ,  G06F2009/45579

摘要： In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is "1", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is "0" indicating that the interruption is not acceptable by the VM, the interruption conrol mask of the corresponding dedicated real interruption priority order is also "0" and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.

公开(公告)号：US4885681A

公开(公告)日：1989-12-05

申请号：US691909

申请日：1985-01-16

申请人： Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto

发明人： Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F12/08 ,  G06F12/10 ,  G06F13/10

CPC分类号： G06F13/10 ,  G06F9/45558 ,  G06F2009/45579

摘要： In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is "0", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is "0" indicating that the interruption is not acceptable by the VM, the interruption control mask of the corresponding dedicated real interruption priority order is also "0" and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.

摘要翻译： 在能够在一个实际计算机系统下同时运行至少一个操作系统（OS）的虚拟机系统（VMS）和用于控制VMS的控制程序（VMCP）的情况下，目的是减少模拟VM I / Os通过直接I / O执行。 实际子信道控制块的VM信息区域具有包含表示子信道为专用的标志的状态字段。 当标志为“0”时，这意味着该子信道专用于该VM，并且该VMCP的子信道调度是不必要的。 由于真正的中断优先级顺序专用于VM，因此只有VM的I / O中断请求被排队到该专用优先级顺序的实际中断请求队列中，并且避免了该实际中断优先级顺序的VM的混合。 当VM上的OS的中断优先级顺序的中断控制掩码为“0”，表示VM不能接受中断时，相应的专用实际中断优先级顺序的中断控制掩码也为“0”，并且 硬件中断不会发生。 因此，中断由硬件保留，并且避免VMCP对VM的I / O中断保持。

公开(公告)号：US5392409A

公开(公告)日：1995-02-21

申请号：US851629

申请日：1992-03-16

申请人： Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto ,  Taro Inoue ,  Shunji Tanaka

发明人： Hidenori Umeno ,  Takashige Kubo ,  Nobutaka Hagiwara ,  Hiroaki Sato ,  Hideo Sawamoto ,  Taro Inoue ,  Shunji Tanaka

IPC分类号： G06F9/455 ,  G06F13/10 ,  G06F12/00

CPC分类号： G06F13/10 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583

摘要： In a computer system having a central processing unit, a main storage and at least one I/O device, a plurality of operating systems (OS) can simultaneously run under the control of a control program. For executing an I/O instruction using a central processing unit, a plurality of resident areas of said main storage which do not overlap one another are assigned, under the control of the control program, to the plurality of OSs as main memories therefore, respectively. In responding to an I/O instruction issued by a running one of said plural OSs, an address of said main memory assigned to said running OS which participates in an I/Oo operation requested by said I/O instruction is determined without intervention of the control program, and the address is translated into an address of the main storage of the computer system without intervention of said control program. The I/O operation is then executed by using the address resulting from said address translation.

摘要翻译： 在具有中央处理单元，主存储器和至少一个I / O设备的计算机系统中，多个操作系统（OS）可以在控制程序的控制下同时运行。 为了使用中央处理单元执行I / O指令，在控制程序的控制下，分别将不相互重叠的所述主存储器的多个驻留区域分别作为主存储器分配给作为主存储器的多个OS 。 在响应由所述多个OS中运行的一个OS发出的I / O指令时，确定分配给所述运行OS的所述主存储器的参与I / O指令请求的I / Oo操作的地址， 控制程序，并且该地址被转换成计算机系统的主存储器的地址，而不需要所述控制程序的干预。 然后通过使用由所述地址转换产生的地址来执行I / O操作。

公开(公告)号：US4802084A

公开(公告)日：1989-01-31

申请号：US827545

申请日：1986-02-10

申请人： Hiroshi Ikegaya ,  Hidenori Umeno ,  Takashige Kubo ,  Yoshio Ukai ,  Nobuyoshi Sugama

发明人： Hiroshi Ikegaya ,  Hidenori Umeno ,  Takashige Kubo ,  Yoshio Ukai ,  Nobuyoshi Sugama

IPC分类号： G06F12/10 ,  G06F12/06

CPC分类号： G06F12/1036

摘要： In order to carry out address translation which can reduce an overhead of the VMCP to support a virtual storage, a flag indicating a common segment in the virtual machine and a system identifier are held in a TLB, and a VM identifier is held in a segment table origin stack. For the common segment, a current VM identifier is compared with the VM identifier in the segment table origin stack to determine validity of a TLB entry, and for a non-common segment, a system identifier read from the segment table origin stack is compared with the system identifier in the TLB entry to determine validity of the TLB entry.

摘要翻译： 为了执行可以减少VMCP的开销以支持虚拟存储的地址转换，在TLB中保持指示虚拟机中的公共段的标志和系统标识符，并且将VM标识符保存在段 表起源栈。 对于公共段，将当前VM标识符与段表原始栈中的VM标识符进行比较，以确定TLB条目的有效性，并且对于非公共段，从段表原始堆栈读取的系统标识符与 TLB条目中的系统标识符，以确定TLB条目的有效性。

公开(公告)号：US4882690A

公开(公告)日：1989-11-21

申请号：US911461

申请日：1986-09-25

申请人： Takao Shinsha ,  Masato Morita ,  Yoshinori Sakataya ,  Yoji Tsuchiya ,  Mitsuhiro Hikosaka ,  Junji Koshishita ,  Keiho Akiyama ,  Takashige Kubo

发明人： Takao Shinsha ,  Masato Morita ,  Yoshinori Sakataya ,  Yoji Tsuchiya ,  Mitsuhiro Hikosaka ,  Junji Koshishita ,  Keiho Akiyama ,  Takashige Kubo

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A logic design automation system examines correspondence relationship among sublogics in intermediate gate-level logic (containing neither physical design information nor manually optimized logic design information) produced from updated functional-level logic and current gate-level logic (containing the above information) to identify corresponding sublogics and non-corresponding sublogics of the gate-level logics with reference to primary input/output signals and input/output gates. For the corresponding sublogics, the corresponding sublogics of the current gate-level logic are selected, and for the non-corresponding sublogics, the non-corresponding sublogics of the intermediate gate-level logic are selected. The selected sublogics are combined to synthesize updated gate-level logic which preserved therein the physical design information and the manually optimized logic design information for portions of the current gate-level logic which need not be modified.

摘要翻译： 逻辑设计自动化系统检查从更新的功能级逻辑和当前门级逻辑（包含上述信息）产生的中间门级逻辑（不包含物理设计信息或手动优化的逻辑设计信息）的子学习之间的对应关系，以识别 参考主要输入/输出信号和输入/输出门的门级逻辑的相应子语义和非对应子语义。 对于相应的子代码，选择当前门级逻辑的相应子代码，并且对于非对应的子代码，选择中间门级逻辑的非对应子语义。 所选择的子实体被组合以合成更新的门级逻辑，其中保留了不需要修改的当前门级逻辑的部分的物理设计信息和手动优化的逻辑设计信息。

公开(公告)号：US4703422A

公开(公告)日：1987-10-27

申请号：US687160

申请日：1984-12-28

申请人： Toshiyuki Kinoshita ,  Toshiaki Arai ,  Takao Sato ,  Takashige Kubo ,  Yasufumi Yoshizawa ,  Hiromichi Mori

发明人： Toshiyuki Kinoshita ,  Toshiaki Arai ,  Takao Sato ,  Takashige Kubo ,  Yasufumi Yoshizawa ,  Hiromichi Mori

IPC分类号： G06F12/08 ,  G06F9/50 ,  G06F12/12 ,  G06F13/00

CPC分类号： G06F9/5016 ,  G06F12/122

摘要： In a memory hierarchy system having two or more hierarchy storages of different access speeds and programs and/or data to be loaded on the hierarchy storages, an activity information acquisition unit and a display unit are provided to present information regarding selection of programs and/or data to be loaded on a higher level in memory hierarchy, a unit is provided which automatically decides loading of the programs and/or data on the higher level and executes reallocation of the programs and/or data on the basis of the information, and a unit is provided which permits the user to change the loading by using a user command. The user can make full use of these units during execution of the memory hierarchy control. In an embodiment, priority for the programs and/or data to be loaded on the higher level is calculated and decided. The programs and/or data are written into the real storage in accordance with their priority to increase the real storage hit rate upon occurrence of a next request for loading.

摘要翻译： 在具有不同访问速度的两个或多个层次存储器和要加载在层级存储器上的程序和/或数据的存储器层次系统中，提供活动信息获取单元和显示单元以呈现关于程序选择和/或 要在存储器层级中的较高级别上加载的数据，提供了一个单元，其自动地决定上级程序和/或数据的加载，并且基于该信息执行程序和/或数据的重新分配，并且 提供了允许用户通过使用用户命令改变负载的单元。 用户可以在执行存储器层级控制时充分利用这些单元。 在一个实施例中，计算并确定要在较高级上加载的程序和/或数据的优先级。 根据其优先级将程序和/或数据写入真实存储器，以在下一次加载请求发生时增加真实的存储命中率。

公开(公告)号：US4991082A

公开(公告)日：1991-02-05

申请号：US924028

申请日：1986-10-28

申请人： Yasufumi Yoshizawa ,  Taketoshi Sakuraba ,  Toshiaki Arai ,  Toshiyuki Kinoshita ,  Minoru Shibamiya ,  Takashige Kubo

发明人： Yasufumi Yoshizawa ,  Taketoshi Sakuraba ,  Toshiaki Arai ,  Toshiyuki Kinoshita ,  Minoru Shibamiya ,  Takashige Kubo

IPC分类号： G06F12/10

CPC分类号： G06F12/109 ,  G06F2212/656

摘要： An area boundary between a system common area and a job private area is set at any page boundary independently from a segment boundary, and for the segment (boundary segment) containing the area boundary, a page table is prepared for each virtual address space. Thus, virtual pages which are not used as the system common area in the bondary segment can be used by jobs as job private areas.The real page is fixedly allocated to the virtual page belonging to the system common area in the boundary segment. Thus, it is not necessary to simultaneously update page tables for the system common area. Those virtual pages may be subjects of dynamic allocation of the virtual storage.

摘要翻译： 系统公共区域和作业专用区域之间的区域边界被设置在独立于段边界的任何页边界处，并且对于包含区域边界的段（边界段），为每个虚拟地址空间准备页表。 因此，不用作债券部门中的系统公共区域的虚拟页面可以由作为作业私人区域的作业使用。 真实页面被固定地分配给属于边界段中的系统公共区域的虚拟页面。 因此，不需要同时更新系统公共区域的页表。 这些虚拟页面可以是虚拟存储器的动态分配的主题。

公开(公告)号：US4891773A

公开(公告)日：1990-01-02

申请号：US42233

申请日：1987-04-24

申请人： Kimio Ooe ,  Nobutaka Amano ,  Takashige Kubo ,  Kaoru Moriwaki

发明人： Kimio Ooe ,  Nobutaka Amano ,  Takashige Kubo ,  Kaoru Moriwaki

IPC分类号： G06F11/25 ,  G06F17/50

CPC分类号： G06F17/5022

摘要： In a logic simulation method for performing logic simulation of a logic circuit including a circuit with unknown internal logic, the circuit itself with the unknown internal logic is used. The internal status of the circuit is set at an objective status using the interrupt operation afforded by the circuit and thereafter, input signal value is applied to the circuit to obtain a resultant output. For other logic circuits without unknown internal logic, software logic simulation is performed. During such software logic simulation, the actual circuit with unknown internal logic is called.

摘要翻译： 在用于执行包括具有未知内部逻辑的电路的逻辑电路的逻辑模拟的逻辑模拟方法中，使用具有未知内部逻辑的电路本身。 使用由电路提供的中断操作将电路的内部状态设置为客观状态，此后，将输入信号值施加到电路以获得合成输出。 对于没有未知内部逻辑的其他逻辑电路，执行软件逻辑仿真。 在这种软件逻辑仿真期间，称为具有未知内部逻辑的实际电路。

公开(公告)号：US4717844A

公开(公告)日：1988-01-05

申请号：US833266

申请日：1986-02-27

申请人： Kazumasa Shima ,  Syunpei Kawasaki ,  Takashige Kubo

发明人： Kazumasa Shima ,  Syunpei Kawasaki ,  Takashige Kubo

IPC分类号： H01L21/82 ,  H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17708

摘要： A programmable logic array circuit which assumes terms which are not implicants to be DON'T CARE terms, and which produces a logic function having decreased number of product terms; and which has a logic function which eliminates the terms that have been regarded to be DON'T CARE terms.

摘要翻译： 一种可编程逻辑阵列电路，其假定不涉及不关心术语的术语，并且产生具有减少的产品项数量的逻辑功能; 并且具有消除被认为是不关心术语的术语的逻辑功能。