Method and apparatus for testing a logic circuit using parallel to
serial and serial to parallel conversion
    9.
    发明授权
    Method and apparatus for testing a logic circuit using parallel to serial and serial to parallel conversion 失效
    使用并行串行和并行转换来测试逻辑电路的方法和装置

    公开(公告)号:US4553090A

    公开(公告)日:1985-11-12

    申请号:US171273

    申请日:1980-07-23

    CPC分类号: G01R31/318558 G06F2201/88

    摘要: A system for testing a logic circuit having a plurality of flip-flops associated with a scanning path between scanning-in and scanning-out terminals thereof and a combination circuit including logic gates is disclosed. In the system, parallel input data is transformed to serial data by a shift register, and the serial data is set in the flip-flops, while serial output data is transformed to parallel data by the shift register. The data is then output in parallel.

    摘要翻译: 公开了一种用于测试具有与其扫描输出端和扫出端之间的扫描路径相关联的多个触发器的逻辑电路和包括逻辑门的组合电路的系统。 在系统中,并行输入数据由移位寄存器变换为串行数据,串行数据设置在触发器中,串行输出数据由移位寄存器变换为并行数据。 然后数据并行输出。