公开(公告)号：US20120299189A1

公开(公告)日：2012-11-29

申请号：US13425530

申请日：2012-03-21

申请人： Shingo NAKAJIMA

发明人： Shingo NAKAJIMA

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L23/5226 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

摘要翻译： 当形成第一布线和/或第二布线时，在第一布线和/或覆盖存储单元阵列外部的下电极层的一部分的第二布线形成连接部。 在连接部上形成有蚀刻抑制部。 形成接触孔，其中蚀刻抑制部分的部分达到连接部分，并且另一部分通过在包括蚀刻抑制部分的范围内对层压体进行蚀刻而到达下电极层。 层叠体包括绝缘层，第一布线，存储单元层，第二布线和蚀刻抑制部。 接触层通过将导电材料埋入接触孔而形成。

公开(公告)号：US20100038617A1

公开(公告)日：2010-02-18

申请号：US12540896

申请日：2009-08-13

申请人： Shingo NAKAJIMA ,  Eiji ITO ,  Mitsuhiro NOGUCHI

发明人： Shingo NAKAJIMA ,  Eiji ITO ,  Mitsuhiro NOGUCHI

IPC分类号： H01L47/00 ,  H01L21/36

CPC分类号： H01L27/24

摘要： A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.

摘要翻译： 一种具有设置在第一绝缘体上并沿第一方向延伸的第一布线层的半导体存储器件和在第一布线层上以柱形形式设置的非易失性存储单元， 元件和可变电阻元件串联连接。 可变电阻元件的电阻值根据施加到其上的电压或电流而变化。 阻挡层设置在存储单元上并且被配置在面内方向上。 导电层设置在阻挡层上并且被配置在面内方向上。 第二绝缘体设置在第一绝缘体上并且覆盖存储单元，阻挡层和导电层的侧表面。 第二布线层设置在导电层上并沿第二方向延伸。