公开(公告)号：US5680068A

公开(公告)日：1997-10-21

申请号：US546108

申请日：1995-10-20

申请人： Shinji Ochi ,  Yasunori Tanaka ,  Tomohiro Fujisaki

发明人： Shinji Ochi ,  Yasunori Tanaka ,  Tomohiro Fujisaki

IPC分类号： H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03L5/00

CPC分类号： H03K19/00361

摘要： There is provided a semiconductor integrated circuit including an output circuit having a first buffer section to which a first power supply voltage is applied and an input signal is supplied to amplify and output the input signal, and a second buffer section to which a second power supply voltage is applied and a signal output from said first buffer section is supplied to amplify and output the signal outside through an output terminal, a switching element which has two terminals respectively connected to said output terminal and a ground voltage terminal and receives a control signal to change a conductive resistance, and a bias circuit for receiving the input signal or a signal output from said first buffer section, generating a control signal, and supplying the control signal to said switching element to control the conductive resistance of said switching element so as not to allow a potential of said output terminal to exceed a predetermined value.

摘要翻译： 提供了一种半导体集成电路，包括：输出电路，其具有施加第一电源电压的第一缓冲部分，并且提供输入信号以放大和输出输入信号;第二缓冲部分，第二电源 电压被施加，从第一缓冲器部分输出的信号通过输出端子放大并输出到外部，开关元件具有分别连接到所述输出端子的两个端子和接地电压端子，并接收控制信号 改变导电电阻;以及偏置电路，用于接收所述输入信号或从所述第一缓冲器部分输出的信号，产生控制信号，并将所述控制信号提供给所述开关元件，以控制所述开关元件的导电电阻，使得不 以允许所述输出端子的电位超过预定值。

公开(公告)号：US5796299A

公开(公告)日：1998-08-18

申请号：US759703

申请日：1996-12-06

申请人： Toshikazu Sei ,  Tomohiro Fujisaki

发明人： Toshikazu Sei ,  Tomohiro Fujisaki

IPC分类号： H01L21/82 ,  H01L27/118 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/173 ,  H01L25/00

CPC分类号： H01L27/11898

摘要： There is provided a semiconductor integrated circuit having peripheral cell array including I/O cells and power supply cells, the cell array comprising first type cells having second level wiring layers consisting of a reference power supply (GND) wiring and a first power supply wiring, and second type cells having the second level wiring layers consisting of the reference power supply wiring, first and second power supply wirings. The second type cells are arranged in a predetermined area collectively and first and/or second power supply voltage are supplied to predetermined cells, through the second level wiring layers.

摘要翻译： 提供具有包括I / O单元和电源单元的外围单元阵列的半导体集成电路，该单元阵列包括具有由参考电源（GND）布线和第一电源布线组成的第二电平布线层的第一类型单元， 以及具有由基准电源布线，第一和第二电源配线构成的第二电平配线层的第二电池。 第二类型单元被集中布置在预定区域中，并且通过第二层布线层将第一和/或第二电源电压提供给预定单元。