公开(公告)号：US07109500B2

公开(公告)日：2006-09-19

申请号：US10509230

申请日：2003-03-20

申请人： Shinji Omori ,  Kaoru Koike ,  Shigeru Moriya ,  Isao Ashida

发明人： Shinji Omori ,  Kaoru Koike ,  Shigeru Moriya ,  Isao Ashida

IPC分类号： H01L21/027 ,  G03F9/00

CPC分类号： G03F1/20 ,  H01J2237/31794

摘要： A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high accuracy are provided. A mask pattern correction method, a mask production method, a mask produced thereby and a production method of a semiconductor device using the mask include a step of creating first position data indicating positions of a plurality of marks when supporting a first thin film having the marks in a state where a first surface directs upward, a step of creating second position data indicating mark positions when supporting the first thin film in a state where a second surface directs upward, a step of obtaining a transfer function for converting the first position data to the second position data, and a step of correcting a mask pattern as a shape of exposure beam transmission portions formed on a second thin film by using an inverse function of the transfer function.

摘要翻译： 能够通过重力防止图案的位置偏离掩模的位置偏移的掩模图案校正方法，能够以高精度形成精细图案的半导体器件的掩模制造方法，掩模和制造方法， 提供。 掩模图案校正方法，掩模制造方法，由此制备的掩模和使用掩模的半导体器件的制造方法包括：当支撑具有标记的第一薄膜时，创建指示多个标记的位置的第一位置数据的步骤 在第一面向上方的状态下，在第二面向上方的状态下支撑第一薄膜时，形成指示标记位置的第二位置数据的步骤，获得将第一位置数据变换为 第二位置数据，以及通过使用传递函数的反函数将掩模图案校正为形成在第二薄膜上的曝光光束透射部分的形状的步骤。

公开(公告)号：US20050124078A1

公开(公告)日：2005-06-09

申请号：US10509230

申请日：2003-03-20

申请人： Shinji Omori ,  Kaoru Koike ,  Shigeru Moriya ,  Isao Ashida

发明人： Shinji Omori ,  Kaoru Koike ,  Shigeru Moriya ,  Isao Ashida

IPC分类号： G03F1/20 ,  G03F1/68 ,  G03F7/20 ,  H01L21/027 ,  H01L21/66 ,  G01R31/26

CPC分类号： G03F1/20 ,  H01J2237/31794

摘要： A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high accuracy are provided. A mask pattern correction method, a mask production method, a mask produced thereby and a production method of a semiconductor device using the mask include a step of creating first position data indicating positions of a plurality of marks when supporting a first thin film having the marks in a state where a first surface directs upward, a step of creating second position data indicating mark positions when supporting the first thin film in a state where a second surface directs upward, a step of obtaining a transfer function for converting the first position data to the second position data, and a step of correcting a mask pattern as a shape of exposure beam transmission portions formed on a second thin film by using an inverse function of the transfer function.

摘要翻译： 能够通过重力防止图案的位置偏离掩模的位置偏移的掩模图案校正方法，能够以高精度形成精细图案的半导体器件的掩模制造方法，掩模和制造方法， 提供。 掩模图案校正方法，掩模制造方法，由此制备的掩模和使用掩模的半导体器件的制造方法包括：当支撑具有标记的第一薄膜时，创建指示多个标记的位置的第一位置数据的步骤 在第一面向上方的状态下，在第二面向上方的状态下支撑第一薄膜时，形成指示标记位置的第二位置数据的步骤，获得将第一位置数据变换为 第二位置数据，以及通过使用传递函数的反函数将掩模图案校正为形成在第二薄膜上的曝光光束透射部分的形状的步骤。

公开(公告)号：US07102243B2

公开(公告)日：2006-09-05

申请号：US10712333

申请日：2003-11-13

申请人： Kaoru Koike ,  Shigeru Moriya

发明人： Kaoru Koike ,  Shigeru Moriya

IPC分类号： H01L23/544

CPC分类号： G03F1/20 ,  H01J2237/0435 ,  H01J2237/31791 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

公开(公告)号：US20060151710A1

公开(公告)日：2006-07-13

申请号：US10534917

申请日：2003-11-13

申请人： Shinji Omori ,  Shigeru Moriya ,  Shinichiro Nohdo

发明人： Shinji Omori ,  Shigeru Moriya ,  Shinichiro Nohdo

IPC分类号： H01J3/14 ,  A61N5/00

CPC分类号： B82Y40/00 ,  B82Y10/00 ,  G03F1/20 ,  H01J37/304 ,  H01J37/3174

摘要： To provide an exposure apparatus and an exposure method able to correct an image-placement error during an exposure which is unable to decrease only by correcting electron beam description data of a mask pattern, and a semiconductor device manufacturing method used the same, wherein an image placement R2 of a mask is measured at an inversion posture against an exposure posture (ST7), the measured image placement R2 is corrected with considering a pattern displacement caused by gravity at the exposure posture and a first correction data Δ1 is prepared based on a difference of the corrected image placement and a designed data (ST10), and an exposure is performed by deflecting charged particle beam to correct a position of a pattern to be exposed to a subject based on the first correction data Δ1 (ST13).

摘要翻译： 为了提供一种曝光装置和曝光方法，能够通过校正掩膜图案的电子束描述数据而不能减小曝光期间的图像放置误差，以及使用其的半导体器件制造方法，其中图像 以与曝光姿势相反的反转姿势（ST7）测量掩模的放置R 2，考虑由曝光姿势引起的重力引起的图案位移，并且准备第一校正数据Delta 1来校正测量图像布置R 2 基于校正图像放置的差异和设计数据（ST10），并且通过基于第一校正数据Delta 1来对带电粒子束进行偏转来校正要暴露于对象的图案的位置来执行曝光（ ST 13）。

公开(公告)号：US07057300B2

公开(公告)日：2006-06-06

申请号：US10843485

申请日：2004-05-12

申请人： Shigeru Moriya ,  Shinji Omori

发明人： Shigeru Moriya ,  Shinji Omori

IPC分类号： H01L23/544

CPC分类号： G03F1/20 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/31794 ,  H01L21/0334 ,  Y10S438/975

摘要： To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

公开(公告)号：US06955993B2

公开(公告)日：2005-10-18

申请号：US10467123

申请日：2002-12-04

申请人： Shinji Omori ,  Shigeru Moriya

发明人： Shinji Omori ,  Shigeru Moriya

IPC分类号： G03C5/00 ,  G03F1/20 ,  G03F1/68 ,  G03F9/00 ,  H01L21/302

CPC分类号： G03F1/20 ,  H01J2237/31788 ,  Y10S438/942

摘要： A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines 4 formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.

摘要翻译： 提供能够通过TTR系统对准并具有高强度的掩模，其制造方法以及具有高图案精度的半导体器件的制造方法。 一种具有条形网格线4的模板掩模，其通过在膜上的四个子区域A至D中蚀刻硅晶片而形成，所述四个子区域A至D围绕膜的中心对称排列，并且将所有栅格线连接到 其他格栅线或膜周围的硅晶片（支撑框架），其制造方法以及使用该掩模的半导体器件的制造方法。

公开(公告)号：US20050174553A1

公开(公告)日：2005-08-11

申请号：US11103809

申请日：2005-04-12

申请人： Kaoru Koike ,  Shigeru Moriya

发明人： Kaoru Koike ,  Shigeru Moriya

IPC分类号： G03F1/20 ,  G03F7/20 ,  G03F9/00 ,  H01J37/305 ,  H01L21/027 ,  H01L23/544 ,  G03B27/42

CPC分类号： G03F1/20 ,  H01J2237/0435 ,  H01J2237/31791 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

摘要翻译： 掩模坯料具有要形成掩模电路图案的多个图案形成区域和不形成任何掩模电路图案的支撑区域。 支撑区域用于在分离多个图案形成区域的同时保持多个图案形成区域。 支撑区域具有第一和第二对准标记。 基于第一对准标记进行由掩模毛坯制成的掩模的曝光，并且基于第二对准标记进行用于在其上形成电路图案的基板的曝光。 利用这种结构，可以以低成本高精度地制造用于带电粒子束减小和分割转印曝光的掩模，并且可以通过使用掩模高度准确地执行基板的曝光。

公开(公告)号：US07456031B2

公开(公告)日：2008-11-25

申请号：US10534917

申请日：2003-11-13

申请人： Shinji Omori ,  Shigeru Moriya ,  Shinichiro Nohdo

发明人： Shinji Omori ,  Shigeru Moriya ,  Shinichiro Nohdo

IPC分类号： H01L31/26 ,  H01L21/66

CPC分类号： B82Y40/00 ,  B82Y10/00 ,  G03F1/20 ,  H01J37/304 ,  H01J37/3174

摘要： To provide an exposure apparatus and an exposure method able to correct an image-placement error during an exposure which is unable to decrease only by correcting electron beam description data of a mask pattern, and a semiconductor device manufacturing method used the same, wherein an image placement R2 of a mask is measured at an inversion posture against an exposure posture (ST7), the measured image placement R2 is corrected with considering a pattern displacement caused by gravity at the exposure posture and a first correction data Δ1 is prepared based on a difference of the corrected image placement and a designed data (ST10), and an exposure is performed by deflecting charged particle beam to correct a position of a pattern to be exposed to a subject based on the first correction data Δ1 (ST13).

摘要翻译： 为了提供一种曝光装置和曝光方法，能够通过校正掩膜图案的电子束描述数据而不能减小曝光期间的图像放置误差，以及使用其的半导体器件制造方法，其中图像 以与曝光姿势相反的反转姿势（ST7）测量掩模的放置R 2，考虑由曝光姿势引起的重力引起的图案位移，并且准备第一校正数据Delta 1来校正测量图像布置R 2 基于校正图像放置的差异和设计数据（ST10），并且通过基于第一校正数据Delta 1来对带电粒子束进行偏转来校正要暴露于对象的图案的位置来执行曝光（ ST 13）。

公开(公告)号：US20070054202A1

公开(公告)日：2007-03-08

申请号：US11594878

申请日：2006-11-09

申请人： Shigeru Moriya ,  Shinji Omori

发明人： Shigeru Moriya ,  Shinji Omori

IPC分类号： G21K5/00 ,  G03F1/00

CPC分类号： G03F1/20 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/31794 ,  H01L21/0334 ,  Y10S438/975

摘要： To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

公开(公告)号：US07144178B2

公开(公告)日：2006-12-05

申请号：US10689098

申请日：2003-10-21

申请人： Shigeru Moriya ,  Shinji Omori

发明人： Shigeru Moriya ,  Shinji Omori

IPC分类号： G03F1/00

CPC分类号： G03F1/20 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/31794 ,  H01L21/0334 ,  Y10S438/975

摘要： To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.