公开(公告)号：US07877581B2

公开(公告)日：2011-01-25

申请号：US10726470

申请日：2003-12-02

申请人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

发明人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30025 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30032

摘要： A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

摘要翻译： 提供了网络应用处理器。 处理器包括被配置为接收数据分组的输入套接字。 处理器包括用于保存指令的存储器和被配置为访问与处理级相关联的数据结构的电路。 被配置为访问数据结构的电路使得能够从存储器单元访问单个操作数。 提供了算术逻辑单元（ALU）。 包括用于对准由ALU处理的操作数的电路。 用于对准操作数的电路使操作数与最低有效位对齐，其中对准操作数的电路向操作数提供扩展以允许ALU处理不同大小的操作数。

公开(公告)号：US20050099841A1

公开(公告)日：2005-05-12

申请号：US10726470

申请日：2003-12-02

申请人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

发明人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G11C11/00

CPC分类号： G06F9/30025 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30032

摘要： A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

摘要翻译： 提供了网络应用处理器。 处理器包括被配置为接收数据分组的输入套接字。 处理器包括用于保存指令的存储器和被配置为访问与处理级相关联的数据结构的电路。 被配置为访问数据结构的电路使得能够从存储器单元访问单个操作数。 提供了算术逻辑单元（ALU）。 包括用于对准由ALU处理的操作数的电路。 用于对准操作数的电路使得操作数被最低有效位对准，其中用于对准操作数的电路向操作数提供扩展以允许ALU处理不同大小的操作数。

公开(公告)号：US07320013B2

公开(公告)日：2008-01-15

申请号：US10726427

申请日：2003-12-02

申请人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

发明人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

IPC分类号： G06F5/01

CPC分类号： G06F5/01 ,  G06F7/49994

摘要： A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.

摘要翻译： 提供了一种透明地呈现不同大小的待处理操作数的方法。 该方法通过提供具有第一位宽的第一操作数来启动。 然后，确定与处理器相关联的第二操作数的位宽度。 第二个操作数的位宽比第一个操作数大。 接下来，通过将第一操作数的最低有效位与具有等于第二操作数的位大小的变换操作数的最低位位置对齐来变换第一操作数。 然后，变换的操作数的位被符号扩展并以允许进位传播的方式填充。 接下来，将变换的操作数传送到处理器。 还提供了用于移位操作数和处理器的方法。

公开(公告)号：US20080320544A1

公开(公告)日：2008-12-25

申请号：US12124931

申请日：2008-05-21

申请人： Neeraj Kashalkar ,  Christopher den Haan ,  Hongfan Wang ,  Sushil Kering ,  Stephen A. Mueller

发明人： Neeraj Kashalkar ,  Christopher den Haan ,  Hongfan Wang ,  Sushil Kering ,  Stephen A. Mueller

IPC分类号： H04N7/173

CPC分类号： H04N21/8166 ,  H04H40/18 ,  H04N21/4436 ,  H04N21/64315 ,  Y02D70/168

摘要： A hardware-implemented video broadcasting receiver is described. The hardware-implemented video broadcasting receiver includes a radio frequency (RF) tuner, a demodulator connected to the RF tuner, link layer logic connected to the demodulator, and a power manager connected to the RF tuner, the demodulator and the link layer logic. The power manager is configured to receive delta-T values extracted from a transport stream by the link layer logic, to determine whether each of the RF tuner, the demodulator and the link layer logic can be powered down based on the delta-T values, and to power down the RF tuner, the demodulator and the link layer logic based on the determination, thereby reducing the average power consumed by the video broadcasting receiver.

摘要翻译： 描述硬件实现的视频广播接收机。 硬件实现的视频广播接收机包括射频（RF）调谐器，连接到RF调谐器的解调器，连接到解调器的链路层逻辑以及连接到RF调谐器，解调器和链路层逻辑的电源管理器。 功率管理器被配置为从链路层逻辑接收从传输流提取的Δ-T值，以确定RF调谐器，解调器和链路层逻辑中的每一个是否可以基于Δ-T值被掉电， 并且基于该确定来关闭RF调谐器，解调器和链路层逻辑，从而降低视频广播接收机消耗的平均功率。

公开(公告)号：US20090007207A1

公开(公告)日：2009-01-01

申请号：US12040650

申请日：2008-02-29

申请人： Neeraj Kashalkar ,  Hongfan Wang ,  Stephen Mueller

发明人： Neeraj Kashalkar ,  Hongfan Wang ,  Stephen Mueller

IPC分类号： H04J3/00 ,  H04N5/44

CPC分类号： H04H40/18 ,  H04H20/30 ,  H04H20/426 ,  H04N21/4382 ,  H04N21/64315

摘要： A hardware-implemented video broadcasting receiver is described that is capable handling back-to-back and parallel time slices in an efficient manner, thereby providing improved receiver performance. In one implementation, the hardware-implemented video broadcasting receiver is capable of handling back-to-back time slices of up to 2 Megabits (Mbits) each and, depending upon the MPE-FEC frame size associated with each time slice, up to 8 parallel time slices or up to 4 parallel time slices transmitted back-to-back with 4 other parallel time slices. The hardware-implemented video broadcasting receiver advantageously permits more efficient and flexible use of the available spectrum and increases interoperability with other DVB-H compliant equipment.

摘要翻译： 描述了能够以有效的方式处理背靠背和并行时间片的硬件实现的视频广播接收机，从而提供改进的接收机性能。 在一个实现中，硬件实现的视频广播接收机能够处理每个高达2兆比特（Mbits）的背对背时间片，并且根据与每个时间片相关联的MPE-FEC帧大小最多8 平行的时间片或最多4个并行时间片，其中四个并行时间片背对背传播。 硬件实现的视频广播接收器有利地允许更有效和灵活地使用可用频谱，并增加与其他符合DVB-H标准的设备的互操作性。

公开(公告)号：US20090003370A1

公开(公告)日：2009-01-01

申请号：US11847839

申请日：2007-08-30

申请人： Sushil Kering ,  Neeraj Kashalkar ,  Stephen A. Mueller

发明人： Sushil Kering ,  Neeraj Kashalkar ,  Stephen A. Mueller

IPC分类号： H04L12/56

CPC分类号： H04L1/0045

摘要： A system and method for improved performance by a DVB-H receiver is described that allows good Internet Protocol (IP) packets in a Multiprotocol Encapsulation-Forward Error Correction (MPE-FEC) frame to be salvaged even when there are other IP packets in the frame that may have bytes in error after the performance of MPE-FEC operations. To achieve this, the system and method provides a means for ascertaining where IP packets loaded into a memory begin and end in a manner that can be relied upon even when individual bytes of the IP packets, such as certain bytes of the IP packet header used to determine total packet length, may be in error.

摘要翻译： 描述了一种通过DVB-H接收机改进性能的系统和方法，其允许在多协议封装前向纠错（MPE-FEC）帧中的良好互联网协议（IP）分组被抢救，即使当在其中存在其他IP分组时 在执行MPE-FEC操作后可能会出现错误字节的帧。 为了实现这一点，系统和方法提供了一种用于确定加载到存储器中的IP分组何时开始和结束的方式，即使在IP分组的各个字节（例如，使用的IP分组报头的某些字节） 确定总包长度，可能是错误的。